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-rw-r--r--src/soc/intel/alderlake/chip.h2
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 5f556c8e96..b9be02bf1d 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -436,6 +436,8 @@ struct soc_intel_alderlake_config {
* 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT.
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
+
+ uint16_t MaxDramSpeed;
};
typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 2d0f6daef4..698cff67ce 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -136,6 +136,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
{
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
+ if (config->MaxDramSpeed)
+ m_cfg->DdrFreqLimit = config->MaxDramSpeed;
}
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,