diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra210/Makefile.inc | 9 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/mmu_operations.c | 35 |
2 files changed, 35 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 0593f06e52..fb38d38409 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -161,14 +161,11 @@ endif # BL31 component is placed towards the end of 32-bit address space. This assumes # that TrustZone memory is placed at the end of 32-bit address space. Within the -# TZ memory, we place TTB at the beginning and then remaining space can be used -# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component -# by: +# TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB +# towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by: # 0x1000 = end of 32-bit address space in MiB # 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB -# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB) -# = skip TTB buffer and get base address of BL31 -BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20)) +BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20)) BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 # MTC fw diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index dd7437c3d7..5578933514 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -18,6 +18,7 @@ */ #include <arch/mmu.h> +#include <assert.h> #include <memrange.h> #include <soc/addressmap.h> #include <soc/mmu_operations.h> @@ -69,15 +70,43 @@ void tegra210_mmu_init(void) { uintptr_t tz_base_mib; size_t tz_size_mib; + uintptr_t ttb_base_mib; size_t ttb_size_mib; struct memranges *map = &t210_mmap_ranges; tegra210_memrange_init(map); mainboard_add_memory_ranges(map); - /* Place page tables at the base of the trust zone region. */ + /* + * Place page tables at the end of the trust zone region. + * TZDRAM layout is as follows: + * + * +--------------------------+ <----+DRAM_END + * | | + * | | + * | | + * +--------------------------+ <----+0x100000000 + * | | + * | coreboot page tables | + * +--------------------------+ + * | | + * | BL32 | + * +--------------------------+ + * | | + * | BL31 | + * +--------------------------+ <----+TZDRAM_BASE + * | | + * | | + * | | + * | | + * +--------------------------+ <----+DRAM_BASE + * + */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - tz_base_mib *= MiB; + + assert(tz_size_mib > CONFIG_TTB_SIZE_MB); + ttb_base_mib = (tz_base_mib + tz_size_mib - CONFIG_TTB_SIZE_MB) * MiB; + ttb_size_mib = CONFIG_TTB_SIZE_MB * MiB; - mmu_init(map, (void *)tz_base_mib, ttb_size_mib); + mmu_init(map, (void *)ttb_base_mib, ttb_size_mib); mmu_enable(); } |