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-rw-r--r--src/mainboard/google/mancomb/dsdt.asl11
-rw-r--r--src/mainboard/google/mancomb/variants/baseboard/devicetree.cb5
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/mancomb/dsdt.asl b/src/mainboard/google/mancomb/dsdt.asl
index 7b8982a645..73a2ea5da1 100644
--- a/src/mainboard/google/mancomb/dsdt.asl
+++ b/src/mainboard/google/mancomb/dsdt.asl
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <variant/ec.h>
+
DefinitionBlock (
"dsdt.aml",
"DSDT",
@@ -13,4 +15,13 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl>
#include <soc.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
}
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index db21dd4e26..c4ef3f546b 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -42,5 +42,10 @@ chip soc/amd/cezanne
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
end
+ device ref lpc_bridge on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
end # domain
end # chip soc/amd/cezanne