diff options
Diffstat (limited to 'src')
8 files changed, 129 insertions, 6 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index b69a5e9466..e9dccd8090 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -3,13 +3,17 @@ if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_CANNONLAKE + select DRIVERS_I2C_GENERIC + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select SOC_INTEL_CANNONLAKE config MAINBOARD_DIR string @@ -45,6 +49,13 @@ config IFD_BIN_PATH depends on HAVE_IFD_BIN default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.bin" +config INCLUDE_SND_MAX98357_DA7219_NHLT + bool "Include blobs for audio with MAX98357_DA7219" + select NHLT_DMIC_4CH_16B + select NHLT_DMIC_2CH_16B + select NHLT_DA7219 + select NHLT_MAX98357 + config ME_BIN_PATH string depends on HAVE_ME_BIN diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c index 855d368d56..316485d6e6 100644 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -13,9 +13,12 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <nhlt.h> #include <soc/gpio.h> +#include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -28,8 +31,33 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + static void mainboard_enable(device_t dev) { + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc index 9fb63f5f43..0ad298b5f4 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += nhlt.c diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index f50c5b7e85..44632e910d 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -48,8 +48,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), /* A19 : ISH_GP_1 */ PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), - /* A20 : ISH_GP_2 */ - PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1), + /* A20 : aduio codec irq */ + PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP), /* A21 : ISH_GP_3 */ PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), /* A22 : ISH_GP_4 */ @@ -149,15 +149,19 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTSB_SML0BALERTB */ PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), /* D17 : DMIC_CLK_1_SNDW3_CLK */ + PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), /* D18 : DMIC_DATA_1_SNDW3_DATA */ + PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), /* D20 : DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), /* D21 : SPI1_IO_2 */ PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), /* D22 : SPI1_IO_3 */ PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), /* D23 : SPP_MCLK */ - + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCIE_0_SATAGP_0 */ #if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), @@ -242,7 +246,9 @@ static const struct pad_config gpio_table[] = { /* H4 : I2C2_SDA */ /* H5 : I2C2_SCL */ /* H6 : I2C3_SDA */ + PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1), /* H7 : I2C3_SCL */ + PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1), /* H8 : I2C4_SDA */ /* H9 : I2C4_SCL */ /* H10 : I2C5_SDA_ISH_I2C2_SDA */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h index 88d39332c5..056c57b813 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -28,4 +28,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c new file mode 100644 index 0000000000..f8647d7011 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +{ + /* 1-dmic configuration */ + if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 1)) + printk(BIOS_ERR, "Added 1CH DMIC array.\n"); + /* 2-dmic configuration */ + if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + /* 4-dmic configuration */ + if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Added 4CH DMIC array.\n"); + +#if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT) + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); +#endif +} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 36318f4d80..8502048880 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -90,7 +90,25 @@ chip soc/intel/cannonlake end # I2C 0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.3 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -126,7 +144,13 @@ chip soc/intel/cannonlake end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 50ae8ba02c..a42494c71d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/gpio.h> #include <soc/pch.h> #include <soc/gpio_defs.h> #include <soc/pci_devs.h> |