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-rw-r--r--src/northbridge/intel/sandybridge/Makefile.inc1
-rw-r--r--src/northbridge/intel/sandybridge/early_dmi.c226
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c1
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h1
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c209
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
6 files changed, 236 insertions, 204 deletions
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index cc4ddaf861..ba55466026 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -29,6 +29,7 @@ romstage-y += common.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
+romstage-y += early_dmi.c
romstage-y += raminit.c
romstage-y += raminit_common.c
romstage-y += raminit_sandy.c
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c
new file mode 100644
index 0000000000..db49040dc1
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/early_dmi.c
@@ -0,0 +1,226 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void early_init_dmi(void)
+{
+ volatile u32 tmp;
+ int i;
+
+ DMIBAR32(0x0914) |= 0x80000000;
+ DMIBAR32(0x0934) |= 0x80000000;
+
+ for (i = 0; i < 4; i++) {
+ DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff;
+ DMIBAR32(0x0a04 + (i << 4)) |= 0x800;
+ }
+ DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000;
+
+ for (i = 0; i < 2; i++) {
+ DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff;
+ DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff;
+ }
+
+ DMIBAR32(0x090c) &= 0xfe1fffff;
+ DMIBAR32(0x092c) &= 0xfe1fffff;
+
+ tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec
+ DMIBAR32(0x0904) = 0x7a1842ec;
+ tmp = DMIBAR32(0x090c); // !!! = 0x00000208
+ DMIBAR32(0x090c) = 0x00000128;
+ tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec
+ DMIBAR32(0x0924) = 0x7a1842ec;
+ tmp = DMIBAR32(0x092c); // !!! = 0x00000208
+ DMIBAR32(0x092c) = 0x00000128;
+ tmp = DMIBAR32(0x0700); // !!! = 0x46139008
+ DMIBAR32(0x0700) = 0x46139008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x46139008
+ DMIBAR32(0x0720) = 0x46139008;
+ tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008
+ DMIBAR32(0x0c04) = 0x2e680008;
+ tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec
+ DMIBAR32(0x0904) = 0x3a1842ec;
+ tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec
+ DMIBAR32(0x0924) = 0x3a1842ec;
+ tmp = DMIBAR32(0x0910); // !!! = 0x00006300
+ DMIBAR32(0x0910) = 0x00004300;
+ tmp = DMIBAR32(0x0930); // !!! = 0x00006300
+ DMIBAR32(0x0930) = 0x00004300;
+ tmp = DMIBAR32(0x0a00); // !!! = 0x03042010
+ DMIBAR32(0x0a00) = 0x03042018;
+ tmp = DMIBAR32(0x0a10); // !!! = 0x03042010
+ DMIBAR32(0x0a10) = 0x03042018;
+ tmp = DMIBAR32(0x0a20); // !!! = 0x03042010
+ DMIBAR32(0x0a20) = 0x03042018;
+ tmp = DMIBAR32(0x0a30); // !!! = 0x03042010
+ DMIBAR32(0x0a30) = 0x03042018;
+ tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08
+ DMIBAR32(0x0c00) = 0x29700c08;
+ tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0
+ DMIBAR32(0x0a04) = 0x0c0718f0;
+ tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0
+ DMIBAR32(0x0a14) = 0x0c0718f0;
+ tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0
+ DMIBAR32(0x0a24) = 0x0c0718f0;
+ tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0
+ DMIBAR32(0x0a34) = 0x0c0718f0;
+ tmp = DMIBAR32(0x0900); // !!! = 0x50000000
+ DMIBAR32(0x0900) = 0x50000000;
+ tmp = DMIBAR32(0x0920); // !!! = 0x50000000
+ DMIBAR32(0x0920) = 0x50000000;
+ tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff
+ DMIBAR32(0x0908) = 0x51ffffff;
+ tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff
+ DMIBAR32(0x0928) = 0x51ffffff;
+ tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
+ DMIBAR32(0x0a00) = 0x03042018;
+ tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
+ DMIBAR32(0x0a10) = 0x03042018;
+ tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
+ DMIBAR32(0x0a20) = 0x03042018;
+ tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
+ DMIBAR32(0x0a30) = 0x03042018;
+ tmp = DMIBAR32(0x0700); // !!! = 0x46139008
+ DMIBAR32(0x0700) = 0x46139008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x46139008
+ DMIBAR32(0x0720) = 0x46139008;
+ tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec
+ DMIBAR32(0x0904) = 0x3a1846ec;
+ tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec
+ DMIBAR32(0x0924) = 0x3a1846ec;
+ tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
+ DMIBAR32(0x0a00) = 0x03042018;
+ tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
+ DMIBAR32(0x0a10) = 0x03042018;
+ tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
+ DMIBAR32(0x0a20) = 0x03042018;
+ tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
+ DMIBAR32(0x0a30) = 0x03042018;
+ tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff
+ DMIBAR32(0x0908) = 0x51ffffff;
+ tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff
+ DMIBAR32(0x0928) = 0x51ffffff;
+ tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08
+ DMIBAR32(0x0c00) = 0x29700c08;
+ tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400
+ DMIBAR32(0x0c0c) = 0x00063400;
+ tmp = DMIBAR32(0x0700); // !!! = 0x46139008
+ DMIBAR32(0x0700) = 0x46339008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x46139008
+ DMIBAR32(0x0720) = 0x46339008;
+ tmp = DMIBAR32(0x0700); // !!! = 0x46339008
+ DMIBAR32(0x0700) = 0x45339008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x46339008
+ DMIBAR32(0x0720) = 0x45339008;
+ tmp = DMIBAR32(0x0700); // !!! = 0x45339008
+ DMIBAR32(0x0700) = 0x453b9008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x45339008
+ DMIBAR32(0x0720) = 0x453b9008;
+ tmp = DMIBAR32(0x0700); // !!! = 0x453b9008
+ DMIBAR32(0x0700) = 0x45bb9008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x453b9008
+ DMIBAR32(0x0720) = 0x45bb9008;
+ tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008
+ DMIBAR32(0x0700) = 0x45fb9008;
+ tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008
+ DMIBAR32(0x0720) = 0x45fb9008;
+ tmp = DMIBAR32(0x0914); // !!! = 0x9021a080
+ DMIBAR32(0x0914) = 0x9021a280;
+ tmp = DMIBAR32(0x0934); // !!! = 0x9021a080
+ DMIBAR32(0x0934) = 0x9021a280;
+ tmp = DMIBAR32(0x0914); // !!! = 0x9021a280
+ DMIBAR32(0x0914) = 0x9821a280;
+ tmp = DMIBAR32(0x0934); // !!! = 0x9021a280
+ DMIBAR32(0x0934) = 0x9821a280;
+ tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
+ DMIBAR32(0x0a00) = 0x03242018;
+ tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
+ DMIBAR32(0x0a10) = 0x03242018;
+ tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
+ DMIBAR32(0x0a20) = 0x03242018;
+ tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
+ DMIBAR32(0x0a30) = 0x03242018;
+ tmp = DMIBAR32(0x0258); // !!! = 0x40000600
+ DMIBAR32(0x0258) = 0x60000600;
+ tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec
+ DMIBAR32(0x0904) = 0x2a1846ec;
+ tmp = DMIBAR32(0x0914); // !!! = 0x9821a280
+ DMIBAR32(0x0914) = 0x98200280;
+ tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec
+ DMIBAR32(0x0924) = 0x2a1846ec;
+ tmp = DMIBAR32(0x0934); // !!! = 0x9821a280
+ DMIBAR32(0x0934) = 0x98200280;
+ tmp = DMIBAR32(0x022c); // !!! = 0x00c26460
+ DMIBAR32(0x022c) = 0x00c2403c;
+
+ early_pch_init_native_dmi_pre();
+
+ /* Write once settings. */
+ DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
+ (2 << 0) | // 5GT/s
+ (2 << 12) | // L0s 128 ns to less than 256 ns
+ (2 << 15); // L1 2 us to less than 4 us
+
+ DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+ while (DMIBAR16(DMILSTS) & TXTRN)
+ ;
+
+ DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+ while (DMIBAR16(DMILSTS) & TXTRN)
+ ;
+
+ const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
+ const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500;
+
+ printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
+ /*
+ * Virtual Channel resources must match settings in RCBA!
+ *
+ * Channel Vp and Vm are documented in
+ * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel
+ * Pentium Processor Family, and Desktop Intel Celeron Processor Family
+ * Vol. 2"
+ */
+
+ /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */
+ DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
+ /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */
+ DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
+ /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */
+ DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1);
+ /* Channel m: Enable, Set ID to 0, map TC7 to VCm */
+ DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1);
+
+ /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */
+ DMIBAR8(DMIPVCCAP1) |= 1;
+
+ early_pch_init_native_dmi_post();
+
+ /*
+ * BIOS Requirement: Check if DMI VC Negotiation was successful.
+ * Wait for virtual channels negotiation pending.
+ */
+ while (DMIBAR16(DMIVC0RSTS) & VC0NP)
+ ;
+ while (DMIBAR16(DMIVC1RSTS) & VC1NP)
+ ;
+ while (DMIBAR16(DMIVCPRSTS) & VCPNP)
+ ;
+ while (DMIBAR16(DMIVCMRSTS) & VCMNP)
+ ;
+}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2ebeaf0dca..f67d61f973 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -315,6 +315,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
}
early_pch_init_native();
+ early_init_dmi();
early_thermal_init();
/* try to find timings in MRC cache */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 77f2ead74e..77165f6931 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -220,6 +220,7 @@ void sandybridge_early_initialization(void);
void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
void northbridge_romstage_finalize(int s3resume);
+void early_init_dmi(void);
#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 76f1447e8a..e74c3043f0 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -70,158 +70,8 @@ write_iobp(u32 address, u32 val)
tmp = RCBA8(IOBPS); // call wait_iobp() instead here?
}
-static void
-init_dmi (void)
+void early_pch_init_native_dmi_pre(void)
{
- volatile u32 tmp;
- int i;
-
- DMIBAR32(0x0914) |= 0x80000000;
- DMIBAR32(0x0934) |= 0x80000000;
-
- for (i = 0; i < 4; i++) {
- DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff;
- DMIBAR32(0x0a04 + (i << 4)) |= 0x800;
- }
- DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000;
-
- for (i = 0; i < 2; i++) {
- DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff;
- DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff;
- }
-
- DMIBAR32(0x090c) &= 0xfe1fffff;
- DMIBAR32(0x092c) &= 0xfe1fffff;
-
- tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec
- DMIBAR32(0x0904) = 0x7a1842ec;
- tmp = DMIBAR32(0x090c); // !!! = 0x00000208
- DMIBAR32(0x090c) = 0x00000128;
- tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec
- DMIBAR32(0x0924) = 0x7a1842ec;
- tmp = DMIBAR32(0x092c); // !!! = 0x00000208
- DMIBAR32(0x092c) = 0x00000128;
- tmp = DMIBAR32(0x0700); // !!! = 0x46139008
- DMIBAR32(0x0700) = 0x46139008;
- tmp = DMIBAR32(0x0720); // !!! = 0x46139008
- DMIBAR32(0x0720) = 0x46139008;
- tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008
- DMIBAR32(0x0c04) = 0x2e680008;
- tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec
- DMIBAR32(0x0904) = 0x3a1842ec;
- tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec
- DMIBAR32(0x0924) = 0x3a1842ec;
- tmp = DMIBAR32(0x0910); // !!! = 0x00006300
- DMIBAR32(0x0910) = 0x00004300;
- tmp = DMIBAR32(0x0930); // !!! = 0x00006300
- DMIBAR32(0x0930) = 0x00004300;
- tmp = DMIBAR32(0x0a00); // !!! = 0x03042010
- DMIBAR32(0x0a00) = 0x03042018;
- tmp = DMIBAR32(0x0a10); // !!! = 0x03042010
- DMIBAR32(0x0a10) = 0x03042018;
- tmp = DMIBAR32(0x0a20); // !!! = 0x03042010
- DMIBAR32(0x0a20) = 0x03042018;
- tmp = DMIBAR32(0x0a30); // !!! = 0x03042010
- DMIBAR32(0x0a30) = 0x03042018;
- tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08
- DMIBAR32(0x0c00) = 0x29700c08;
- tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0
- DMIBAR32(0x0a04) = 0x0c0718f0;
- tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0
- DMIBAR32(0x0a14) = 0x0c0718f0;
- tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0
- DMIBAR32(0x0a24) = 0x0c0718f0;
- tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0
- DMIBAR32(0x0a34) = 0x0c0718f0;
- tmp = DMIBAR32(0x0900); // !!! = 0x50000000
- DMIBAR32(0x0900) = 0x50000000;
- tmp = DMIBAR32(0x0920); // !!! = 0x50000000
- DMIBAR32(0x0920) = 0x50000000;
- tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff
- DMIBAR32(0x0908) = 0x51ffffff;
- tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff
- DMIBAR32(0x0928) = 0x51ffffff;
- tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
- DMIBAR32(0x0a00) = 0x03042018;
- tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
- DMIBAR32(0x0a10) = 0x03042018;
- tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
- DMIBAR32(0x0a20) = 0x03042018;
- tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
- DMIBAR32(0x0a30) = 0x03042018;
- tmp = DMIBAR32(0x0700); // !!! = 0x46139008
- DMIBAR32(0x0700) = 0x46139008;
- tmp = DMIBAR32(0x0720); // !!! = 0x46139008
- DMIBAR32(0x0720) = 0x46139008;
- tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec
- DMIBAR32(0x0904) = 0x3a1846ec;
- tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec
- DMIBAR32(0x0924) = 0x3a1846ec;
- tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
- DMIBAR32(0x0a00) = 0x03042018;
- tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
- DMIBAR32(0x0a10) = 0x03042018;
- tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
- DMIBAR32(0x0a20) = 0x03042018;
- tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
- DMIBAR32(0x0a30) = 0x03042018;
- tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff
- DMIBAR32(0x0908) = 0x51ffffff;
- tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff
- DMIBAR32(0x0928) = 0x51ffffff;
- tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08
- DMIBAR32(0x0c00) = 0x29700c08;
- tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400
- DMIBAR32(0x0c0c) = 0x00063400;
- tmp = DMIBAR32(0x0700); // !!! = 0x46139008
- DMIBAR32(0x0700) = 0x46339008;
- tmp = DMIBAR32(0x0720); // !!! = 0x46139008
- DMIBAR32(0x0720) = 0x46339008;
- tmp = DMIBAR32(0x0700); // !!! = 0x46339008
- DMIBAR32(0x0700) = 0x45339008;
- tmp = DMIBAR32(0x0720); // !!! = 0x46339008
- DMIBAR32(0x0720) = 0x45339008;
- tmp = DMIBAR32(0x0700); // !!! = 0x45339008
- DMIBAR32(0x0700) = 0x453b9008;
- tmp = DMIBAR32(0x0720); // !!! = 0x45339008
- DMIBAR32(0x0720) = 0x453b9008;
- tmp = DMIBAR32(0x0700); // !!! = 0x453b9008
- DMIBAR32(0x0700) = 0x45bb9008;
- tmp = DMIBAR32(0x0720); // !!! = 0x453b9008
- DMIBAR32(0x0720) = 0x45bb9008;
- tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008
- DMIBAR32(0x0700) = 0x45fb9008;
- tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008
- DMIBAR32(0x0720) = 0x45fb9008;
- tmp = DMIBAR32(0x0914); // !!! = 0x9021a080
- DMIBAR32(0x0914) = 0x9021a280;
- tmp = DMIBAR32(0x0934); // !!! = 0x9021a080
- DMIBAR32(0x0934) = 0x9021a280;
- tmp = DMIBAR32(0x0914); // !!! = 0x9021a280
- DMIBAR32(0x0914) = 0x9821a280;
- tmp = DMIBAR32(0x0934); // !!! = 0x9021a280
- DMIBAR32(0x0934) = 0x9821a280;
- tmp = DMIBAR32(0x0a00); // !!! = 0x03042018
- DMIBAR32(0x0a00) = 0x03242018;
- tmp = DMIBAR32(0x0a10); // !!! = 0x03042018
- DMIBAR32(0x0a10) = 0x03242018;
- tmp = DMIBAR32(0x0a20); // !!! = 0x03042018
- DMIBAR32(0x0a20) = 0x03242018;
- tmp = DMIBAR32(0x0a30); // !!! = 0x03042018
- DMIBAR32(0x0a30) = 0x03242018;
- tmp = DMIBAR32(0x0258); // !!! = 0x40000600
- DMIBAR32(0x0258) = 0x60000600;
- tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec
- DMIBAR32(0x0904) = 0x2a1846ec;
- tmp = DMIBAR32(0x0914); // !!! = 0x9821a280
- DMIBAR32(0x0914) = 0x98200280;
- tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec
- DMIBAR32(0x0924) = 0x2a1846ec;
- tmp = DMIBAR32(0x0934); // !!! = 0x9821a280
- DMIBAR32(0x0934) = 0x98200280;
- tmp = DMIBAR32(0x022c); // !!! = 0x00c26460
- DMIBAR32(0x022c) = 0x00c2403c;
-
/* Link Capabilities Register */
RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) |
(3 << 10) | // L0s and L1 entry supported
@@ -230,45 +80,11 @@ init_dmi (void)
RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16);
RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2;
+}
- /* Write once settings. */
- DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
- (2 << 0) | // 5GT/s
- (2 << 12) | // L0s 128 ns to less than 256 ns
- (2 << 15); // L1 2 us to less than 4 us
-
- DMIBAR8(DMILCTL) |= 0x20; // Retrain link
- while (DMIBAR16(DMILSTS) & TXTRN)
- ;
-
- DMIBAR8(DMILCTL) |= 0x20; // Retrain link
- while (DMIBAR16(DMILSTS) & TXTRN)
- ;
-
- const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
- const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500;
-
- printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
- /*
- * Virtual Channel resources must match settings in RCBA!
- *
- * Channel Vp and Vm are documented in
- * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel
- * Pentium Processor Family, and Desktop Intel Celeron Processor Family
- * Vol. 2"
- */
-
- /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */
- DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
- /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */
- DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
- /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */
- DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1);
- /* Channel m: Enable, Set ID to 0, map TC7 to VCm */
- DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1);
-
- /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */
- DMIBAR8(DMIPVCCAP1) |= 1;
+void early_pch_init_native_dmi_post(void)
+{
+ volatile u32 tmp;
tmp = RCBA32(0x0050); // !!! = 0x01200654
RCBA32(0x0050) = 0x01200654;
@@ -334,19 +150,6 @@ init_dmi (void)
;
while (RCBA16(0x2046) & VCNEGPND)
;
-
- /*
- * BIOS Requirement: Check if DMI VC Negotiation was successful.
- * Wait for virtual channels negotiation pending.
- */
- while (DMIBAR16(DMIVC0RSTS) & VC0NP)
- ;
- while (DMIBAR16(DMIVC1RSTS) & VC1NP)
- ;
- while (DMIBAR16(DMIVCPRSTS) & VCPNP)
- ;
- while (DMIBAR16(DMIVCMRSTS) & VCMNP)
- ;
}
void
@@ -433,8 +236,6 @@ early_pch_init_native (void)
write_iobp(0xec0007b2, 0x04514b5e);
write_iobp(0xec00078c, 0x40000200);
write_iobp(0xec000780, 0x02000020);
-
- init_dmi();
}
static void pch_enable_bars(void)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index fb8238ad4f..faa6822bf2 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -77,6 +77,8 @@ void southbridge_rcba_config(void);
void mainboard_rcba_config(void);
void early_pch_init_native(void);
void early_pch_init(void);
+void early_pch_init_native_dmi_pre(void);
+void early_pch_init_native_dmi_post(void);
struct southbridge_usb_port
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 14:29:03 +0000