diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/device/sd_mmc_ctrlr.h | 21 | ||||
| -rw-r--r-- | src/include/device/sdhci.h | 15 |
2 files changed, 18 insertions, 18 deletions
diff --git a/src/include/device/sd_mmc_ctrlr.h b/src/include/device/sd_mmc_ctrlr.h index b7541da12f..2ca2d0f19a 100644 --- a/src/include/device/sd_mmc_ctrlr.h +++ b/src/include/device/sd_mmc_ctrlr.h @@ -176,16 +176,17 @@ struct sd_mmc_ctrlr { * start at 0x00010000 */ #define DRVR_CAP_4BIT 0x00000001 -#define DRVR_CAP_AUTO_CMD12 0x00000002 -#define DRVR_CAP_HC 0x00000004 -#define DRVR_CAP_HS 0x00000008 -#define DRVR_CAP_HS52 0x00000010 -#define DRVR_CAP_HS200 0x00000020 -#define DRVR_CAP_HS400 0x00000040 -#define DRVR_CAP_ENHANCED_STROBE 0x00000080 -#define DRVR_CAP_REMOVABLE 0x00000100 -#define DRVR_CAP_DMA_64BIT 0x00000200 -#define DRVR_CAP_HS200_TUNING 0x00000400 +#define DRVR_CAP_8BIT 0x00000002 +#define DRVR_CAP_AUTO_CMD12 0x00000004 +#define DRVR_CAP_HC 0x00000008 +#define DRVR_CAP_HS 0x00000010 +#define DRVR_CAP_HS52 0x00000020 +#define DRVR_CAP_HS200 0x00000040 +#define DRVR_CAP_HS400 0x00000080 +#define DRVR_CAP_ENHANCED_STROBE 0x00000100 +#define DRVR_CAP_REMOVABLE 0x00000200 +#define DRVR_CAP_DMA_64BIT 0x00000400 +#define DRVR_CAP_HS200_TUNING 0x00000800 uint32_t b_max; uint32_t timing; diff --git a/src/include/device/sdhci.h b/src/include/device/sdhci.h index f11e589395..a86582d767 100644 --- a/src/include/device/sdhci.h +++ b/src/include/device/sdhci.h @@ -24,14 +24,13 @@ /* Driver specific capabilities */ #define DRVR_CAP_1V8_VDD 0x00010000 #define DRVR_CAP_32BIT_DMA_ADDR 0x00020000 -#define DRVR_CAP_8BIT 0x00040000 -#define DRVR_CAP_BROKEN_R1B 0x00080000 -#define DRVR_CAP_NO_CD 0x00100000 -#define DRVR_CAP_NO_HISPD_BIT 0x00200000 -#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00400000 -#define DRVR_CAP_REG32_RW 0x00800000 -#define DRVR_CAP_SPI 0x01000000 -#define DRVR_CAP_WAIT_SEND_CMD 0x02000000 +#define DRVR_CAP_BROKEN_R1B 0x00040000 +#define DRVR_CAP_NO_CD 0x00080000 +#define DRVR_CAP_NO_HISPD_BIT 0x00100000 +#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00200000 +#define DRVR_CAP_REG32_RW 0x00400000 +#define DRVR_CAP_SPI 0x00800000 +#define DRVR_CAP_WAIT_SEND_CMD 0x01000000 /* ADMA packet descriptor */ struct sdhci_adma { |