3 files changed, 37 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index b0eb693d54..559b8a1bb2 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -24,7 +24,7 @@ romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c
 romstage-y += ../common/emi.c
 romstage-y += irq2axi.c
 romstage-y += l2c_ops.c
-romstage-y += ../common/memory.c
+romstage-y += ../common/memory.c memory.c
 romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
index dde00c23da..c01daf5838 100644
--- a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
@@ -43,6 +43,23 @@ typedef enum {
 	IMP_DRV_MAX,
 } DRAM_IMP_DRV_T;
 
+typedef enum {
+	TYPE_DDR1 = 1,
+	TYPE_DDR2,
+	TYPE_DDR3,
+	TYPE_DDR4,
+	TYPE_DDR5,
+	TYPE_LPDDR2,
+	TYPE_LPDDR3,
+	TYPE_PCDDR3,
+	TYPE_LPDDR4,
+	TYPE_LPDDR4X,
+	TYPE_LPDDR4P,
+	TYPE_LPDDR5,
+	TYPE_LPDDR5X,
+	TYPE_MAX,
+} DRAM_DRAM_TYPE_T;
+
 #define DRAM_DFS_SHU_MAX	DRAM_DFS_SRAM_MAX
 #define DQS_NUMBER_LP5		2
 #define DQ_DATA_WIDTH_LP5	16
diff --git a/src/soc/mediatek/mt8196/memory.c b/src/soc/mediatek/mt8196/memory.c
new file mode 100644
index 0000000000..2689e5a6c3
--- /dev/null
+++ b/src/soc/mediatek/mt8196/memory.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <commonlib/bsd/mem_chip_info.h>
+#include <soc/emi.h>
+
+enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type)
+{
+	switch (lpddr_type) {
+	case TYPE_LPDDR4X:
+		return MEM_CHIP_LPDDR4X;
+	case TYPE_LPDDR5:
+		return MEM_CHIP_LPDDR5;
+	case TYPE_LPDDR5X:
+		return MEM_CHIP_LPDDR5X;
+	default:
+		return MEM_CHIP_UNDEFINED;
+	}
+}