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-rw-r--r--src/mainboard/google/brya/variants/aurash/Makefile.inc10
-rw-r--r--src/mainboard/google/brya/variants/aurash/fw_config.c44
-rw-r--r--src/mainboard/google/brya/variants/aurash/gpio.c138
-rw-r--r--src/mainboard/google/brya/variants/aurash/memory.c31
-rw-r--r--src/mainboard/google/brya/variants/aurash/overridetree.cb322
-rw-r--r--src/mainboard/google/brya/variants/aurash/ramstage.c72
-rw-r--r--src/mainboard/google/brya/variants/aurash/variant.c13
7 files changed, 628 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/aurash/Makefile.inc b/src/mainboard/google/brya/variants/aurash/Makefile.inc
new file mode 100644
index 0000000000..b799b4d7b8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/aurash/fw_config.c b/src/mainboard/google/brya/variants/aurash/fw_config.c
new file mode 100644
index 0000000000..5302923cd2
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/fw_config.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
+ PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
+ PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
+ PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
+ PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
+ PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
+ PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
+ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+ PAD_NC(GPP_VGPIO_30, NONE),
+ PAD_NC(GPP_VGPIO_31, NONE),
+ PAD_NC(GPP_VGPIO_32, NONE),
+ PAD_NC(GPP_VGPIO_33, NONE),
+ PAD_NC(GPP_VGPIO_34, NONE),
+ PAD_NC(GPP_VGPIO_35, NONE),
+ PAD_NC(GPP_VGPIO_36, NONE),
+ PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+ if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+ printk(BIOS_INFO, "Disable BT offload audio related GPIO pins.\n");
+ gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+ return;
+ }
+
+ if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
+ printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n");
+ gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+ }
+
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/aurash/gpio.c b/src/mainboard/google/brya/variants/aurash/gpio.c
new file mode 100644
index 0000000000..78e1243b8e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/gpio.c
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+ /* A14 : USB_OC1# ==> NC */
+ PAD_NC(GPP_A14, NONE),
+ /* A19 : DDSP_HPD1 ==> NC */
+ PAD_NC(GPP_A19, NONE),
+ /* A20 : DDSP_HPD2 ==> DDIC_DP_HPD4 */
+ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+ /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : DDPC_CTRLDATA ==> NC */
+ PAD_NC(GPP_A22, NONE),
+
+ /* B2 : VRALERT# ==> NC */
+ PAD_NC(GPP_B2, NONE),
+ /* B3 : PROC_GP2 ==> EMMC_PERST_L */
+ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+
+ /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
+ PAD_CFG_GPO(GPP_D14, 1, DEEP),
+
+ /* E1 : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */
+ PAD_CFG_GPI(GPP_E1, NONE, DEEP),
+ /* E2 : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E20 : DDP2_CTRLCLK ==> DDIC_DP_CTRCLK */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+ /* E21 : DDP2_CTRLDATA ==> DDIC_DP_CTRLDATA */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+ /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+
+ /* R6 : I2S2_TXD ==> NC */
+ PAD_NC(GPP_R6, NONE),
+ /* R7 : I2S2_RXD ==> NC */
+ PAD_NC(GPP_R7, NONE),
+
+ /* GPD11: LANPHYC ==> LAN_DISABLE_N */
+ PAD_CFG_GPO(GPD11, 0, DEEP),
+};
+
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* B3 : PROC_GP2 ==> EMMC_PERST_L */
+ PAD_CFG_GPO(GPP_B3, 0, DEEP),
+ /* B4 : PROC_GP3 ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_B4, 0, DEEP),
+ /*
+ * D1 : ISH_GP1 ==> FP_RST_ODL
+ * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+ * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+ * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+ * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+ * FPMCU not working after a S3 resume. This is a known issue.
+ */
+ PAD_CFG_GPO(GPP_D1, 0, DEEP),
+ /* D2 : ISH_GP2 ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ /* D18 : UART1_TXD ==> SD_PE_RST_L */
+ PAD_CFG_GPO(GPP_D18, 0, PLTRST),
+ /* E15 : RSVD_TP ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* F14 : GSXDIN ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_F14, 1, DEEP),
+ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_H13, 1, DEEP),
+
+ /* CPU PCIe VGPIO for PEG60 */
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+static const struct pad_config romstage_gpio_table[] = {
+ /* B4 : PROC_GP3 ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_B4, 1, DEEP),
+ /* D18 : UART1_TXD ==> SD_PE_RST_L */
+ PAD_CFG_GPO(GPP_D18, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+ *num = ARRAY_SIZE(override_gpio_table);
+ return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(romstage_gpio_table);
+ return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/aurash/memory.c b/src/mainboard/google/brya/variants/aurash/memory.c
new file mode 100644
index 0000000000..ad33e9c9c7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+ .type = MEM_TYPE_DDR4,
+
+ .rcomp = {
+ /* Baseboard uses only 100ohm Rcomp resistors */
+ .resistor = 100,
+
+ /* Baseboard Rcomp target values */
+ .targets = {50, 20, 25, 25, 25},
+ },
+
+ .ect = 1, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_MOBILE,
+
+ .ddr_config = {
+ .dq_pins_interleaved = false,
+ },
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &ddr4_mem_config;
+}
diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb
index 4f2c04a57a..2f773484ab 100644
--- a/src/mainboard/google/brya/variants/aurash/overridetree.cb
+++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb
@@ -1,6 +1,324 @@
+fw_config
+ field USBC0_RETIMER 2 3
+ option USBC0_RETIMER_ABSENT 0
+ option USBC0_RETIMER_PRESENT 1
+ end
+ field STORAGE 4 5
+ option STORAGE_UNKNOWN 0
+ option STORAGE_NVME 1
+ option STORAGE_EMMC 2
+ end
+ field AUDIO 6
+ option AUDIO_UNKNOWN 0
+ option NAU88L25B_I2S 1
+ end
+end
chip soc/intel/alderlake
+ # As per Intel Advisory doc#723158, the change is required to prevent possible
+ # display flickering issue.
+ register "usb2_phy_sus_pg_disable" = "1"
+ # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
+ register "ddi_ports_config" = "{
+ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_1] = DDI_ENABLE_HPD,
+ [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_3] = DDI_ENABLE_HPD,
+ }"
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port2
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
+ register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
+ register "usb3_ports[2]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_de_emp = 0x2B,
+ .tx_downscale_amp = 0x00,
+ }" # Type-A port A2
+ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
+ register "tcc_offset" = "0" # TCC of 100C
+ register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 25,
+ }"
+ register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+ .tdp_pl1_override = 64,
+ }"
+ device domain 0 on
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""SSD""
+ register "options.tsr[1].desc" = ""CPU_VR""
+ register "options.tsr[2].desc" = ""DIMM""
+
+
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
+ }"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ }"
+
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 15000,
+ .max_power = 55000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 55000,
+ .max_power = 55000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ register "oem_data.oem_variables" = "{
+ [0] = 0x1
+ }"
- device domain 0 on
- end
+ device generic 0 alias dptf_policy on end
+ end
+ end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port3 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end # USB4 Port
+ device ref pcie4_0 on
+ # Enable CPU PCIE RP 1 using CLK 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ probe STORAGE STORAGE_NVME
+ probe STORAGE STORAGE_UNKNOWN
+ end # SSD
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end # WiFi
+ device ref i2c0 on
+ chip drivers/i2c/nau8825
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "0"
+ register "jkdet_pull_up" = "0"
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x0C"
+ register "sar_threshold[1]" = "0x1C"
+ register "sar_threshold[2]" = "0x38"
+ register "sar_threshold[3]" = "0x60"
+ register "sar_hysteresis" = "1"
+ register "sar_voltage" = "6"
+ register "sar_compare_time" = "0" # 500ns
+ register "sar_sampling_time" = "0" # 2us
+ register "short_key_debounce" = "2" # 100ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "7" # 512ms
+ device i2c 1a on end
+ end
+ end # Audio Nau8825
+ device ref pcie_rp6 on
+ # Enable PCIe-to-i225 bridge PCIe 6 using clk 4
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 4,
+ .clk_req = 4,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ device pci 00.0 on end
+ end # IntelI225V Ethernet NIC
+ device ref pcie_rp7 on
+ chip drivers/net
+ register "customized_leds" = "0x0482"
+ register "wake" = "GPE0_DW0_07"
+ register "device_index" = "0"
+ register "add_acpi_dma_property" = "true"
+ device pci 00.0 on end
+ end
+ end # RTL8111K Ethernet NIC
+ device ref pcie_rp8 off end #pcie_rp 8 Empty
+ device ref pcie_rp9 off end #pcie_rp 9 Empty
+ device ref pcie_rp10 off end #pcie_rp 10 Empty
+ device ref pcie_rp11 off end #pcie_rp 11 Empty
+ device ref pcie_rp12 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+ register "srcclk_pin" = "1"
+ register "reset_delay_ms" = "50"
+ register "enable_delay_ms" = "20"
+ device generic 0 on
+ probe STORAGE STORAGE_EMMC
+ probe STORAGE STORAGE_UNKNOWN
+ end
+ end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
+ register "pch_pcie_rp[PCH_RP(12)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ probe STORAGE STORAGE_EMMC
+ probe STORAGE STORAGE_UNKNOWN
+ end # BH799BB
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A4 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 NFC""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A3 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A2 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
+ device ref usb2_port7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A1 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
+ device ref usb2_port8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A1 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A2 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
+ device ref usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A3 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A4 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb3_port4 on end
+ end
+ end
+ end
+ end # USB2 and USB3 Port
+ end
end
diff --git a/src/mainboard/google/brya/variants/aurash/ramstage.c b/src/mainboard/google/brya/variants/aurash/ramstage.c
new file mode 100644
index 0000000000..700d173042
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/ramstage.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pci.h>
+#include <drivers/intel/gma/opregion.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
+#include <intelblocks/power_limit.h>
+#include <drivers/intel/dptf/chip.h>
+
+const struct cpu_power_limits limits[] = {
+ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+ { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 25000, 25000, 123000 },
+ { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 25000, 25000, 123000 },
+ { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 25000, 25000, 123000 },
+ { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+ /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+ { PCI_DID_INTEL_ADL_P_ID_10, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_7, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_6, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_5, 28, 135 },
+};
+
+static void update_oem_variables(void)
+{
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+ const struct device *policy_dev = DEV_PTR(dptf_policy);
+ struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+
+ switch (mch_id) {
+ case PCI_DID_INTEL_ADL_P_ID_5:
+ config->oem_data.oem_variables[0] = 0;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_6:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_7:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ case PCI_DID_INTEL_ADL_P_ID_10:
+ config->oem_data.oem_variables[0] = 1;
+ break;
+
+ default:
+ config->oem_data.oem_variables[0] = 1;
+ }
+}
+
+const struct psys_config psys_config = {
+ .efficiency = 97,
+ .psys_imax_ma = 11000,
+ .bj_volts_mv = 19500
+};
+
+void variant_devtree_update(void)
+{
+ size_t total_entries = ARRAY_SIZE(limits);
+ variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+ variant_update_power_limits(limits, total_entries);
+ update_oem_variables();
+}
diff --git a/src/mainboard/google/brya/variants/aurash/variant.c b/src/mainboard/google/brya/variants/aurash/variant.c
new file mode 100644
index 0000000000..951bfe5365
--- /dev/null
+++ b/src/mainboard/google/brya/variants/aurash/variant.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+#include <variant/gpio.h>
+#include <acpi/acpigen.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+ config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+ NAU88L25B_I2S));
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 04:03:39 +0000