2 files changed, 79 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index e5e48bb3a7..547253fef0 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -50,6 +50,9 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
 
+	/* Low power idle table */
+	#include <soc/intel/cannonlake/acpi/lpit.asl>
+
 #if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO)
 	/* Chrome OS Embedded Controller */
 	Scope (\_SB.PCI0.LPCB)
diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl
new file mode 100644
index 0000000000..85158069b6
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/lpit.asl
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+scope(\_SB)
+{
+	Device(LPID) {
+	Name(_ADR, 0x00000000)
+	Name(_CID, EISAID("PNP0D80"))
+	Name(UUID,
+		ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
+		Method(_DSM, 4) {
+			If(Arg0 == ^UUID) {
+			/*
+			 * Enum functions
+			 */
+			If(Arg2 == Zero) {
+				Return(Buffer(One) {
+				       0x60}
+				)
+			}
+			/*
+			 * Function 1.
+			 */
+			If(Arg2 == 1) {
+				Return(Package(5) {
+				       0, Ones, Ones, Ones, Ones}
+				)
+			}
+			/*
+			 * Function 2.
+			 */
+			If(Arg2 == 2) {
+				Return(Buffer(One) {
+				       0x0}
+				)
+			}
+			/*
+			 * Function 3.
+			 */
+			If(Arg2 == 3) {
+			}
+			/*
+			 * Function 4.
+			 */
+			If(Arg2 == 4) {
+			}
+			/*
+			 * Function 5.
+			 */
+			If(Arg2 == 5) {
+				\_SB.PCI0.LPCB.EC0.S0IX(1)
+			}
+			/*
+			 * Function 6.
+			 */
+			If(Arg2 == 6) {
+				\_SB.PCI0.LPCB.EC0.S0IX(0)
+			}
+		}
+		Return(Buffer(One) {0x00})
+		}		// Method(_DSM)
+	}			// device (LPID)
+}				// End Scope(\_SB)