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-rw-r--r--src/soc/mediatek/mt8195/include/soc/iocfg.h1
-rw-r--r--src/soc/mediatek/mt8195/pmif_spi.c6
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/iocfg.h b/src/soc/mediatek/mt8195/include/soc/iocfg.h
index 8ca2f62f62..f3524dcb9a 100644
--- a/src/soc/mediatek/mt8195/include/soc/iocfg.h
+++ b/src/soc/mediatek/mt8195/include/soc/iocfg.h
@@ -63,5 +63,6 @@ check_member(mt8195_iocfg_bm_regs, tdsel_cfg1, 0x110);
enum {
IO_4_MA = 0x9,
+ IO_6_MA = 0x1b,
};
#endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */
diff --git a/src/soc/mediatek/mt8195/pmif_spi.c b/src/soc/mediatek/mt8195/pmif_spi.c
index ddb2175516..eff4a21e89 100644
--- a/src/soc/mediatek/mt8195/pmif_spi.c
+++ b/src/soc/mediatek/mt8195/pmif_spi.c
@@ -10,7 +10,7 @@ DEFINE_BITFIELD(PWRAP_SPI1_DRIVING, 5, 0)
void pmif_spi_iocfg(void)
{
- /* Set SoC SPI IO driving strength to 4 mA */
- SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA);
- SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA);
+ /* Set SoC SPI IO driving strength to 6 mA */
+ SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_6_MA);
+ SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_6_MA);
}