diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 12 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 16 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 20 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 6 |
5 files changed, 28 insertions, 28 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 2d1e86fc09..36d56545da 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -185,7 +185,7 @@ before_romstage: call romstage_main /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. It also contains the information - * for setting up MTTRs. */ + * for setting up MTRRs. */ movl %eax, %ebx post_code(0x2f) @@ -249,23 +249,23 @@ before_romstage: /* Setup stack as indicated by return value from ramstage_main(). */ movl %ebx, %esp - /* Get number of MTTRs. */ + /* Get number of MTRRs. */ popl %ebx movl $MTRRphysBase_MSR(0), %ecx 1: testl %ebx, %ebx jz 1f - /* Low 32 bits of MTTR base. */ + /* Low 32 bits of MTRR base. */ popl %eax - /* Upper 32 bits of MTTR base. */ + /* Upper 32 bits of MTRR base. */ popl %edx /* Write MTRR base. */ wrmsr inc %ecx - /* Low 32 bits of MTTR mask. */ + /* Low 32 bits of MTRR mask. */ popl %eax - /* Upper 32 bits of MTTR mask. */ + /* Upper 32 bits of MTRR mask. */ popl %edx /* Write MTRR mask. */ wrmsr diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 9ed00af632..dcd5dc70ea 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -175,14 +175,14 @@ void romstage_common(const struct romstage_params *params); * torn down. The following values are pushed onto the stack to setup the * MTRRs: * +0: Number of MTRRs - * +4: MTTR base 0 31:0 - * +8: MTTR base 0 63:32 - * +12: MTTR mask 0 31:0 - * +16: MTTR mask 0 63:32 - * +20: MTTR base 1 31:0 - * +24: MTTR base 1 63:32 - * +28: MTTR mask 1 31:0 - * +32: MTTR mask 1 63:32 + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 * ... */ void * asmlinkage romstage_main(unsigned long bist); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2e80cdd..40a396d501 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -108,18 +108,18 @@ static void *setup_romstage_stack_after_car(void) * of physical address bits. */ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - /* The order for each MTTR is value then base with upper 32-bits of + /* The order for each MTRR is value then base with upper 32-bits of * each value coming before the lower 32-bits. The reasoning for * this ordering is to create a stack layout like the following: * +0: Number of MTRRs - * +4: MTTR base 0 31:0 - * +8: MTTR base 0 63:32 - * +12: MTTR mask 0 31:0 - * +16: MTTR mask 0 63:32 - * +20: MTTR base 1 31:0 - * +24: MTTR base 1 63:32 - * +28: MTTR mask 1 31:0 - * +32: MTTR mask 1 63:32 + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 */ /* Cache the ROM as WP just below 4GiB. */ @@ -158,7 +158,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Save the number of MTTRs to setup. Return the stack location + /* Save the number of MTRRs to setup. Return the stack location * pointing to the number of MTRRs. */ slot = stack_push(slot, num_mtrrs); diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 36f94cdf05..0471a9ef9f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -30,7 +30,7 @@ static void cache_ramstage(void) const int addr_det = 0; -/* the fixed and variable MTTRs are power-up with random values, +/* the fixed and variable MTRRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safety. */ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dd404a887f..dbedf0fa9e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -454,7 +454,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, if (var_state->mtrr_index >= bios_mtrrs) printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); if (var_state->mtrr_index >= total_mtrrs) { - printk(BIOS_ERR, "ERROR: Not enough MTTRs available!\n"); + printk(BIOS_ERR, "ERROR: Not enough MTRRs available!\n"); return; } @@ -670,7 +670,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, struct var_mtrr_state var_state; /* The default MTRR cacheability type is determined by calculating - * the number of MTTRs required for each MTTR type as if it was the + * the number of MTRRs required for each MTRR type as if it was the * default. */ var_state.addr_space = addr_space; var_state.above4gb = above4gb; @@ -776,7 +776,7 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type, calc_var_mtrrs_without_hole(&var_state, r); } - /* Clear all remaining variable MTTRs. */ + /* Clear all remaining variable MTRRs. */ for (i = var_state.mtrr_index; i < total_mtrrs; i++) clear_var_mtrr(i); } |