diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 28 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 31 |
2 files changed, 58 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 0c71f221f2..a223542a32 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -111,6 +111,32 @@ static void iio_enable_masks(void) } iio_dmi_en_masks(); } + +static void set_pcu_locks(void) +{ + for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) { + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + + /* configure PCU_CR0_FUN csrs */ + const struct device *cr0_dev = PCU_DEV_CR0(bus); + pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); + + /* configure PCU_CR1_FUN csrs */ + const struct device *cr1_dev = PCU_DEV_CR1(bus); + pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); + + /* configure PCU_CR2_FUN csrs */ + const struct device *cr2_dev = PCU_DEV_CR2(bus); + pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); + + /* configure PCU_CR3_FUN csrs */ + const struct device *cr3_dev = PCU_DEV_CR3(bus); + pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + } + +} + static void chip_final(void *data) { /* Lock SBI */ @@ -127,6 +153,8 @@ static void chip_final(void *data) uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + set_pcu_locks(); + p2sb_hide(); iio_enable_masks(); set_bios_init_completion(); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 46c034c296..54b76b5719 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -23,10 +23,26 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44 +#if !defined(__SIMPLE_DEVICE__) +#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#else +#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#endif + #define PCU_IIO_STACK 1 #define PCU_DEV 30 -#define PCU_CR1_FUN 1 +#define PCU_CR0_FUN 0 +#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) +#define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_P_STATE_LIMITS 0xd8 +#define P_STATE_LIMITS_LOCK BIT(31) +#define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 +#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) +#define PKG_PWR_LIM_LOCK_UPR BIT(31) + +#define PCU_CR1_FUN 1 +#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 @@ -49,6 +65,19 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) +#define PCU_CR1_SAPMCTL 0xb0 +#define SAPMCTL_LOCK_MASK BIT(31) + +#define PCU_CR2_FUN 2 +#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 +#define PP_PWR_LIM_LOCK BIT(31) + +#define PCU_CR3_FUN 3 +#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) +#define PCU_CR3_CONFIG_TDP_CONTROL 0x60 +#define TDP_LOCK BIT(31) + #define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 |