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-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index ff5c83c3af..d7b30c64da 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
}
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
-#if CONFIG(FSP_TYPE_IOT)
+#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/*
* Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
* The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1