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-rw-r--r--src/mainboard/asus/f2a85-m/Kconfig15
-rw-r--r--src/mainboard/asus/f2a85-m/Kconfig.name3
-rw-r--r--src/mainboard/asus/f2a85-m/OemCustomize.c20
-rw-r--r--src/mainboard/asus/f2a85-m/acpi/routing.asl7
-rw-r--r--src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb (renamed from src/mainboard/asus/f2a85-m/devicetree.cb)0
-rw-r--r--src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb172
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c14
7 files changed, 227 insertions, 4 deletions
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index 04eb936008..03c9c28bd3 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
-if BOARD_ASUS_F2A85_M
+if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -25,7 +25,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
- select SUPERIO_ITE_IT8728F
+ select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M
+ select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO
select BOARD_ROMSIZE_KB_8192
select GFXUMA
select HUDSON_DISABLE_IMC
@@ -60,7 +61,8 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
- default "F2A85-M"
+ default "F2A85-M" if BOARD_ASUS_F2A85_M
+ default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO
config HW_MEM_HOLE_SIZEK
hex
@@ -102,4 +104,9 @@ config POST_IO
bool
default n
-endif # BOARD_ASUS_F2A85_M
+config DEVICETREE
+ string
+ default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO
+ default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M
+
+endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name
index af6f62896e..a8aa273954 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig.name
+++ b/src/mainboard/asus/f2a85-m/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_ASUS_F2A85_M
bool "F2A85-M"
+
+config BOARD_ASUS_F2A85_M_PRO
+ bool "F2A85-M PRO"
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 6348d5a9cb..d5452074f4 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -225,6 +225,26 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
*/
PSO_END
};
+#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+/*
+ TODO: is this OK for DDR3 socket FM2?
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ */
+ PSO_END
+};
#endif /* CONFIG_BOARD_ASUS_F2A85_M */
const struct OEM_HOOK OemCustomize = {
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index 0af6b42cad..cc36dcd700 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -46,6 +46,13 @@
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+#if CONFIG_BOARD_ASUS_F2A85_M_PRO
+ Package(){0x000FFFFF, 0, INTA, 0 },
+ Package(){0x000FFFFF, 1, INTB, 0 },
+ Package(){0x000FFFFF, 2, INTC, 0 },
+ Package(){0x000FFFFF, 3, INTD, 0 },
+#endif /* CONFIG_BOARD_ASUS_F2A85_M_PRO */
+
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
index d94244510c..d94244510c 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
new file mode 100644
index 0000000000..238ab5163d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
@@ -0,0 +1,172 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 2.0 on end # Internal Graphics P2P bridge 0x99XX
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 52 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 2
+ device i2c 51 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 3
+ device i2c 53 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # unused
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x780e
+ chip superio/nuvoton/nct5572d
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 off end # LPT1
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2/IR
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on # GPIO6, GPIO7, GPIO8
+ io 0xe0 = 0x7f
+ io 0xe1 = 0x10
+ io 0xe2 = 0x00
+ io 0xe3 = 0x00
+ io 0xe4 = 0xff
+ io 0xe5 = 0xff
+ io 0xe6 = 0xff
+ io 0xe7 = 0xff
+ io 0xec = 0x00
+ io 0xed = 0xff
+ io 0xf4 = 0xff
+ io 0xf5 = 0xff
+ io 0xf6 = 0x00
+ io 0xf7 = 0x00
+ io 0xf8 = 0x00
+ end
+ device pnp 2e.8 on # WDT1, GPIO0, GPIO1
+ io 0x30 = 0x00
+ io 0x60 = 0x00
+ io 0x61 = 0x00
+ io 0xe0 = 0xff
+ io 0xe1 = 0xff
+ io 0xe2 = 0xff
+ io 0xe3 = 0xff
+ io 0xe4 = 0xff
+ io 0xf0 = 0xff
+ io 0xf1 = 0x28
+ io 0xf2 = 0x00
+ io 0xf3 = 0x00
+ io 0xf4 = 0x08
+ io 0xf5 = 0xff
+ io 0xf6 = 0x00
+ io 0xf7 = 0xff
+ end
+ device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8
+ io 0x30 = 0xfe
+ io 0xe0 = 0xff
+ io 0xe1 = 0x90
+ io 0xe2 = 0x00
+ io 0xe3 = 0x00
+ io 0xe4 = 0x7f
+ io 0xe5 = 0x76
+ io 0xe6 = 0x00
+ io 0xe7 = 0x00
+ io 0xe8 = 0x00
+ io 0xe9 = 0x00
+ io 0xea = 0x00
+ io 0xeb = 0x00
+ io 0xee = 0x00
+ io 0xf0 = 0xff
+ io 0xf1 = 0x7b
+ io 0xf2 = 0x00
+ io 0xf4 = 0xff
+ io 0xf5 = 0xef
+ io 0xf6 = 0x00
+ io 0xf7 = 0x00
+ io 0xfe = 0x00
+ end
+ device pnp 2e.a on # ACPI
+ io 0xe6 = 0x4c
+ io 0xe7 = 0x11
+ io 0xf2 = 0x5d
+ end
+ device pnp 2e.b on # Hardware Monitor, Front Panel LED
+ io 0x30 = 0x01
+ io 0x60 = 0x02
+ io 0x61 = 0x90
+ io 0xe2 = 0x7f
+ io 0xe4 = 0xf1
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off # GPIO Push-pull/Open-drain selection
+ io 0xe6 = 7f
+ end
+ device pnp 2e.14 off # PORT80 UART
+ io 0xe0 = 0x00
+ end
+ device pnp 2e.16 off end # Deep Sleep
+ end
+ end #device pci 14.3 # LPC
+
+ device pci 14.4 on end # PCI bridge
+ device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806])
+ device pci 15.0 on end # PCI bridge
+ device pci 15.1 on end # PCI bridge
+ device pci 15.2 on end # PCI bridge # Only present with the original boot firmware
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 90d3fbae32..d66c7d52bd 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -35,15 +35,25 @@
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
+#if CONFIG_BOARD_ASUS_F2A85_M
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
+#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+#endif /* CONFIG_BOARD_ASUS_F2A85_M */
+
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+#if CONFIG_BOARD_ASUS_F2A85_M
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#endif /* CONFIG_BOARD_ASUS_F2A85_M */
static void sbxxx_enable_48mhzout(void)
{
@@ -96,9 +106,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
+#if CONFIG_BOARD_ASUS_F2A85_M
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(GPIO_DEV);
+#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+#endif
console_init();
/* turn on secondary smbus at b20 */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 05:21:54 +0000