5 files changed, 11 insertions, 16 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 1c2ec8400f..5c5179d5cd 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select X86_AMD_FIXED_MTRRS
+	select X86_AMD_INIT_SIPI
 	select ACPI_AMD_HARDWARE_SLEEP_VALUES
 	select COLLECT_TIMESTAMPS_NO_TSC
 	select DRIVERS_I2C_DESIGNWARE
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 5f897fe29d..cc06496326 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -32,6 +32,7 @@
 #include <amdblocks/acpi.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
+#include <soc/cpu.h>
 #include <soc/southbridge.h>
 #include <soc/northbridge.h>
 #include <soc/nvs.h>
@@ -238,10 +239,7 @@ void generate_cpu_entries(struct device *device)
 {
 	int cores, cpu;
 
-	/* Picasso is single node, just report # of cores */
-	cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
-	cores++; /* number of cores is CmpCap+1 */
-
+	cores = get_cpu_count();
 	printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
 
 	/* Generate BSP \_PR.P000 */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 5c2ca432f1..21818e4c88 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2015-2016 Intel Corp.
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -54,10 +54,9 @@ static void pre_mp_init(void)
 	x86_mtrr_check();
 }
 
-static int get_cpu_count(void)
+int get_cpu_count(void)
 {
-	return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK)
-									+ 1;
+	return 1 + (cpuid_ecx(0x80000008) & 0xff);
 }
 
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
@@ -118,22 +117,22 @@ void picasso_init_cpus(struct device *dev)
 	set_warm_reset_flag();
 }
 
-static void model_15_init(struct device *dev)
+static void model_17_init(struct device *dev)
 {
 	check_mca();
 	setup_lapic();
 }
 
 static struct device_operations cpu_dev_ops = {
-	.init = model_15_init,
+	.init = model_17_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x670f00 },
+	{ X86_VENDOR_AMD, 0x810f81 },
 	{ 0, 0 },
 };
 
-static const struct cpu_driver model_15 __cpu_driver = {
+static const struct cpu_driver model_17 __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
 };
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 7bc1810dba..e57d2d3187 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -22,6 +22,7 @@
 #define SOC_EARLY_VMTRR_TEMPRAM 2
 
 void picasso_init_cpus(struct device *dev);
+int get_cpu_count(void);
 void check_mca(void);
 
 #endif /* __PICASSO_CPU_H__ */
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index 667a49eb0c..e423ab1aa7 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -73,10 +73,6 @@
 #define D18F1_VGAEN		0xf4
 # define VGA_ADDR_ENABLE	(1 << 0)
 
-/* D18F5 */
-#define NB_CAPABILITIES2	0x84
-#define   CMP_CAP_MASK		0xff
-
 void amd_initcpuio(void);
 
 void domain_enable_resources(struct device *dev);