diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/baytrail/acpi.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/cpu.c | 32 |
2 files changed, 5 insertions, 30 deletions
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 67e8c0ca89..aae0c9961a 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -354,8 +354,7 @@ static int generate_P_state_entries(int core, int cores_per_package) vid_min = pattrs->iacore_vids[IACORE_LFM]; /* Set P-states coordination type based on MSR disable bit */ - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - coord_type = (msr.lo & SINGLE_PCTL) ? SW_ALL : HW_ALL; + coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; /* Max Non-Turbo Frequency */ clock_max = (ratio_max * pattrs->bclk_khz) / 1000; diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 97d1f04b97..e8f95ae167 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -68,37 +68,16 @@ const struct reg_script package_msr_script[] = { /* Core level MSRs */ const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_POWER_MISC, + ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), REG_SCRIPT_END }; -/* Enable hardware coordination for 2-core, disable for 4-core */ -static void baytrail_set_pstate_coord(void) -{ - const struct pattrs *pattrs = pattrs_get(); - msr_t pmg_cst = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr_t power_misc = rdmsr(MSR_POWER_MISC); - - if (pattrs->num_cpus > 2) { - /* Disable hardware coordination */ - pmg_cst.lo |= SINGLE_PCTL; - power_misc.lo &= ~(ENABLE_ULFM_AUTOCM_MASK | - ENABLE_INDP_AUTOCM_MASK); - } else { - /* Enable hardware coordination */ - pmg_cst.lo &= ~SINGLE_PCTL; - power_misc.lo |= (ENABLE_ULFM_AUTOCM_MASK | - ENABLE_INDP_AUTOCM_MASK); - } - - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, pmg_cst); - wrmsr(MSR_POWER_MISC, power_misc); -} - void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -156,9 +135,6 @@ static void baytrail_core_init(device_t cpu) /* Set core MSRs */ reg_script_run(core_msr_script); - /* Set P-State coordination */ - baytrail_set_pstate_coord(); - /* Set this core to max frequency ratio */ set_max_freq(); } |