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-rw-r--r--src/mainboard/intel/adlrvp/include/baseboard/variants.h1
-rw-r--r--src/mainboard/intel/adlrvp/memory.c62
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c1
-rw-r--r--src/mainboard/intel/adlrvp/spd/Makefile.inc2
-rw-r--r--src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex32
5 files changed, 97 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 8ecfa77b94..af641488c9 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -22,6 +22,7 @@ enum adl_boardid {
ADL_P_DDR4_2 = 0x3F,
/* ADL-M LP4 and LP5 RVPs */
ADL_M_LP4 = 0x1,
+ ADL_M_LP5 = 0x2,
};
/* The next set of functions return the gpio table and fill in the number of
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index f2c378f828..204744f503 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -217,6 +217,66 @@ static const struct mb_cfg adlm_lp4_mem_config = {
.UserBd = BOARD_TYPE_ULT_ULX,
};
+static const struct mb_cfg adlm_lp5_mem_config = {
+ .type = MEM_TYPE_LP5X,
+
+ /* DQ byte map */
+ .lpx_dq_map = {
+ .ddr0 = {
+ .dq0 = { 4, 5, 7, 6, 3, 2, 1, 0, },
+ .dq1 = { 12, 10, 8, 15, 11, 9, 14, 13, },
+ },
+ .ddr1 = {
+ .dq0 = { 1, 0, 2, 3, 7, 4, 5, 6, },
+ .dq1 = { 14, 15, 10, 11, 13, 12, 8, 9, },
+ },
+ .ddr2 = {
+ .dq0 = { 7, 4, 2, 0, 3, 1, 6, 5, },
+ .dq1 = { 14, 13, 15, 12, 8, 9, 10, 11, },
+ },
+ .ddr3 = {
+ .dq0 = { 3, 2, 0, 1, 7, 5, 6, 4, },
+ .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, },
+ },
+ .ddr4 = {
+ .dq0 = { 2, 3, 0, 1, 6, 4, 7, 5, },
+ .dq1 = { 14, 9, 11, 13, 12, 8, 15, 10, },
+ },
+ .ddr5 = {
+ .dq0 = { 4, 7, 3, 1, 5, 2, 6, 0, },
+ .dq1 = { 14, 8, 11, 9, 12, 15, 10, 13, },
+ },
+ .ddr6 = {
+ .dq0 = { 10, 11, 13, 9, 15, 12, 8, 14, },
+ .dq1 = { 2, 4, 7, 0, 6, 3, 5, 1, },
+ },
+ .ddr7 = {
+ .dq0 = { 13, 15, 11, 14, 10, 12, 8, 9, },
+ .dq1 = { 6, 5, 4, 7, 3, 1, 2, 0, },
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .lpx_dqs_map = {
+ .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
+ },
+
+ .ect = false, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_ULT_ULX,
+
+ .lp5x_config = {
+ .ccc_config = 0xff,
+ },
+};
+
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@@ -235,6 +295,8 @@ const struct mb_cfg *variant_memory_params(void)
return &lp5_mem_config;
case ADL_M_LP4:
return &adlm_lp4_mem_config;
+ case ADL_M_LP5:
+ return &adlm_lp5_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);
}
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 7e2638936d..2c611250a5 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -60,6 +60,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
case ADL_P_LP5_1:
case ADL_P_LP5_2:
case ADL_M_LP4:
+ case ADL_M_LP5:
memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
break;
default:
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
index 945e3eb347..5c5c1b4e72 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -2,7 +2,7 @@
SPD_SOURCES = adlrvp_lp4 # 0b000
SPD_SOURCES += adlrvp_m_lp4 # 0b001
-SPD_SOURCES += empty # 0b002
+SPD_SOURCES += adlrvp_m_lp5 # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex
new file mode 100644
index 0000000000..df75f5b2a1
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A F9 08 00 40 00 00 0A 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 23:15:23 +0000