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-rw-r--r--src/soc/intel/common/block/include/intelblocks/tcss.h2
-rw-r--r--src/soc/intel/common/block/tcss/tcss.c18
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h
index 5209858bd5..12400d8c5a 100644
--- a/src/soc/intel/common/block/include/intelblocks/tcss.h
+++ b/src/soc/intel/common/block/include/intelblocks/tcss.h
@@ -146,6 +146,7 @@ extern const struct soc_tcss_ops tcss_ops;
/* Method to configure pads */
void tcss_configure_aux_bias_pads_regbar(const struct typec_aux_bias_pads *pads);
+void ioe_tcss_configure_aux_bias_pads_sbi(const struct typec_aux_bias_pads *pads);
/*
* 1) Initialize TCSS muxes to disconnected state
@@ -163,5 +164,6 @@ const struct tcss_port_map *tcss_get_port_info(size_t *num_ports);
/* Method to validate the Thunderbolt authentication */
bool tcss_valid_tbt_auth(void);
+bool ioe_tcss_valid_tbt_auth(void);
#endif /* _TCSS_H_ */
diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c
index f1a3584400..18fff20fb2 100644
--- a/src/soc/intel/common/block/tcss/tcss.c
+++ b/src/soc/intel/common/block/tcss/tcss.c
@@ -368,6 +368,19 @@ void tcss_configure_aux_bias_pads_regbar(
}
}
+void ioe_tcss_configure_aux_bias_pads_sbi(
+ const struct typec_aux_bias_pads *pads)
+{
+ for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
+ if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) {
+ ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i),
+ calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc));
+ ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i),
+ calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc));
+ }
+ }
+}
+
const struct tcss_port_map *tcss_get_port_info(size_t *num_ports)
{
static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
@@ -424,3 +437,8 @@ bool tcss_valid_tbt_auth(void)
{
return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
}
+
+bool ioe_tcss_valid_tbt_auth(void)
+{
+ return ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
+}