summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_2065x/Kconfig4
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc5
-rw-r--r--src/cpu/intel/model_2065x/bootblock.c64
-rw-r--r--src/mainboard/lenovo/x201/Makefile.inc2
-rw-r--r--src/mainboard/lenovo/x201/early_init.c26
-rw-r--r--src/mainboard/lenovo/x201/romstage.c6
-rw-r--r--src/mainboard/packardbell/ms2290/romstage.c4
-rw-r--r--src/northbridge/intel/nehalem/Kconfig10
-rw-r--r--src/northbridge/intel/nehalem/Makefile.inc2
-rw-r--r--src/northbridge/intel/nehalem/bootblock.c3
-rw-r--r--src/northbridge/intel/nehalem/romstage.c5
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig4
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/ibexpeak/bootblock.c62
-rw-r--r--src/southbridge/intel/ibexpeak/early_pch.c45
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h2
16 files changed, 94 insertions, 152 deletions
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 897a3b4804..572751186e 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -23,10 +23,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
-config BOOTBLOCK_CPU_INIT
- string
- default "cpu/intel/model_2065x/bootblock.c"
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index dde4234521..142842174e 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -15,7 +15,10 @@ smm-y += finalize.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../../x86/early_reset.S
+
postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
deleted file mode 100644
index 399f5e0838..0000000000
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <arch/io.h>
-#include <halt.h>
-
-#include <cpu/intel/microcode/microcode.c>
-
-#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
-#include <southbridge/intel/ibexpeak/pch.h>
-#include "model_2065x.h"
-#else
-#error "CPU must be paired with Intel Ibex Peak southbridge"
-#endif
-
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
- unsigned int type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- /* FIXME: It only support 4G less range */
- msr_t basem, maskm;
- basem.lo = base | type;
- basem.hi = 0;
- wrmsr(MTRR_PHYS_BASE(reg), basem);
- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
- msr_t msr;
-
- disable_cache();
- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
- enable_cache();
-
- /* Enable Variable MTRRs */
- msr.hi = 0x00000000;
- msr.lo = 0x00000800;
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
-static void bootblock_cpu_init(void)
-{
- enable_rom_caching();
- intel_update_microcode_from_cbfs();
-}
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
index f97235612e..548beff15d 100644
--- a/src/mainboard/lenovo/x201/Makefile.inc
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -13,6 +13,8 @@
## GNU General Public License for more details.
##
+bootblock-y += early_init.c
+
smm-y += dock.c
smm-y += smihandler.c
romstage-y += dock.c
diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c
new file mode 100644
index 0000000000..7383381ce9
--- /dev/null
+++ b/src/mainboard/lenovo/x201/early_init.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <ec/acpi/ec.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Enable USB Power. We need to do it early for usbdebug to work. */
+ ec_set_bit(0x3b, 4);
+}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 81752e88ae..99875ed65a 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -24,12 +24,6 @@
#include <southbridge/intel/ibexpeak/pch.h>
#include <northbridge/intel/nehalem/nehalem.h>
-void mainboard_lpc_init(void)
-{
- /* Enable USB Power. We need to do it early for usbdebug to work. */
- ec_set_bit(0x3b, 4);
-}
-
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* Enabled, Current table lookup index, OC map */
{ 1, IF1_557, 0 },
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 61e14f20e3..4d94329b60 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -22,10 +22,6 @@
#include <southbridge/intel/ibexpeak/pch.h>
#include <northbridge/intel/nehalem/nehalem.h>
-void mainboard_lpc_init(void)
-{
-}
-
/* Seems copied from Lenovo Thinkpad x201, might be wrong */
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* Enabled, Current table lookup index, OC map */
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 3adf6987bf..ba9616d31b 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS
select HAVE_DEBUG_RAM_SETUP
+ select C_ENVIRONMENT_BOOTBLOCK
if NORTHBRIDGE_INTEL_NEHALEM
@@ -48,9 +49,12 @@ config DCACHE_RAM_SIZE
hex
default 0x10000
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/intel/nehalem/bootblock.c"
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
config MRC_CACHE_SIZE
hex
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index 3b12bb5854..225f0ce812 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
+bootblock-y += bootblock.c
+
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += smi.c
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index f96ff56a56..46cdef0c47 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -12,8 +12,9 @@
*/
#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c
index 54766de0e7..8188303877 100644
--- a/src/northbridge/intel/nehalem/romstage.c
+++ b/src/northbridge/intel/nehalem/romstage.c
@@ -45,11 +45,6 @@ void mainboard_romstage_entry(void)
/* TODO, make this configurable */
nehalem_early_initialization(NEHALEM_MOBILE);
- pch_pre_console_init();
-
- /* Initialize console device(s) */
- console_init();
-
early_pch_init();
/* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 00eb413d1e..53240cb1df 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -51,10 +51,6 @@ config DRAM_RESET_GATE_GPIO
int
default 60
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/ibexpeak/bootblock.c"
-
config SERIRQ_CONTINUOUS_MODE
bool
default n
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 8c4443ce0e..dc35de561c 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
+bootblock-y += bootblock.c
+
ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c
diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c
index 0086fe3281..599e182a59 100644
--- a/src/southbridge/intel/ibexpeak/bootblock.c
+++ b/src/southbridge/intel/ibexpeak/bootblock.c
@@ -14,7 +14,9 @@
*/
#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
#include "pch.h"
+#include "chip.h"
/*
* Enable Prefetching and Caching.
@@ -32,18 +34,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void)
{
- pci_devfn_t dev = PCH_LPC_DEV;
-
- /* Enable port 80 POST on LPC */
- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-#if 0
- RCBA32(GCS) &= (~0x04);
-#else
- volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
- u32 reg32 = *gcs;
- reg32 = reg32 & ~0x04;
- *gcs = reg32;
-#endif
+ RCBA32(GCS) &= ~4;
}
static void set_spi_speed(void)
@@ -66,12 +57,57 @@ static void set_spi_speed(void)
RCBA8(0x3893) = ssfc;
}
-static void bootblock_southbridge_init(void)
+static void early_lpc_init(void)
+{
+ const struct device *dev = pcidev_on_root(0x1f, 0);
+ const struct southbridge_intel_ibexpeak_config *config = NULL;
+
+ /* Add some default decode ranges:
+ - 0x2e/2f, 0x4e/0x4f
+ - EC/Mouse/KBC 60/64, 62/66
+ - 0x3f8 COMA
+ If more are needed, update in mainboard_lpc_init hook
+ */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ /* Clear PWR_FLR */
+ pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
+ (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
+
+ pci_write_config32(PCH_LPC_DEV, ETR3,
+ pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
+
+ /* Set up generic decode ranges */
+ if (!dev)
+ return;
+ if (dev->chip_info)
+ config = dev->chip_info;
+ if (!config)
+ return;
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+
+void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
+ pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
+
+ early_lpc_init();
}
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c
index ccd8f74431..b76115bf84 100644
--- a/src/southbridge/intel/ibexpeak/early_pch.c
+++ b/src/southbridge/intel/ibexpeak/early_pch.c
@@ -22,45 +22,6 @@
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include "chip.h"
-
-static void early_lpc_init(void)
-{
- const struct device *dev = pcidev_on_root(0x1f, 0);
- const struct southbridge_intel_ibexpeak_config *config = NULL;
-
- /* Add some default decode ranges:
- - 0x2e/2f, 0x4e/0x4f
- - EC/Mouse/KBC 60/64, 62/66
- - 0x3f8 COMA
- If more are needed, update in mainboard_lpc_init hook
- */
- pci_write_config16(PCH_LPC_DEV, LPC_EN,
- CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
- COMA_LPC_EN);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
-
- /* Clear PWR_FLR */
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
- (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
-
- pci_write_config32(PCH_LPC_DEV, ETR3,
- pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
-
- /* Set up generic decode ranges */
- if (!dev)
- return;
- if (dev->chip_info)
- config = dev->chip_info;
- if (!config)
- return;
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
-}
-
static void early_gpio_init(void)
{
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
@@ -80,12 +41,6 @@ static void pch_default_disable(void)
RCBA32(FD2) = 1;
}
-void pch_pre_console_init(void)
-{
- early_lpc_init();
- mainboard_lpc_init();
-}
-
void early_pch_init(void)
{
early_gpio_init();
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 1449ee914d..9e5fa24e9f 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -62,13 +62,11 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
#endif
-void pch_pre_console_init(void);
void early_pch_init(void);
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void pch_setup_cir(int chipset_type);
-void mainboard_lpc_init(void);
enum current_lookup_idx {
IF1_F57 = 0,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 15:49:37 +0000