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-rw-r--r--src/include/cpu/amd/car.h2
-rw-r--r--src/northbridge/amd/pi/Kconfig4
-rw-r--r--src/soc/amd/common/Kconfig8
-rw-r--r--src/soc/amd/common/Makefile.inc7
-rw-r--r--src/soc/amd/common/amd_late_init.c40
-rw-r--r--src/soc/amd/common/cache_as_ram.inc170
-rw-r--r--src/soc/amd/common/heapmanager.c319
-rw-r--r--src/soc/amd/common/spi.c41
-rw-r--r--src/soc/amd/stoneyridge/Kconfig53
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc15
-rw-r--r--src/soc/amd/stoneyridge/acpi/cpu.asl78
-rw-r--r--src/soc/amd/stoneyridge/fixme.c97
-rw-r--r--src/soc/amd/stoneyridge/model_15_init.c135
-rw-r--r--src/vendorcode/amd/Kconfig5
-rw-r--r--src/vendorcode/amd/pi/Kconfig6
-rw-r--r--src/vendorcode/amd/pi/Makefile.inc9
16 files changed, 975 insertions, 14 deletions
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index b4fbd60f74..89f29c2486 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -10,7 +10,7 @@ void post_cache_as_ram(void);
void cache_as_ram_switch_stack(void *stacktop);
void cache_as_ram_new_stack(void);
-#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI
+#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI || CONFIG_SOC_AMD_PI
void disable_cache_as_ram(void);
#endif
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index f5f36f8802..49e915f7d7 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -15,7 +15,9 @@
config NORTHBRIDGE_AMD_PI
bool
- default CPU_AMD_PI
+ default y if CPU_AMD_PI
+ default y if SOC_AMD_PI
+ default n
select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_PI
diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig
index fac3f43565..d4fe1f7523 100644
--- a/src/soc/amd/common/Kconfig
+++ b/src/soc/amd/common/Kconfig
@@ -2,3 +2,11 @@ config SOC_AMD_COMMON
bool
help
common code for AMD SOCs
+
+if SOC_AMD_COMMON
+
+config SOC_AMD_PI
+ bool
+ default n
+
+endif # SOC_AMD_COMMON
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index 689065bd5a..1a4927efaa 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -1,5 +1,12 @@
ifeq ($(CONFIG_SOC_AMD_COMMON),y)
+cpu_incs-y += $(src)/soc/amd/common/cache_as_ram.inc
+
+romstage-y += heapmanager.c
+
+ramstage-y += amd_late_init.c
ramstage-y += amd_pci_util.c
+ramstage-y += heapmanager.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
endif
diff --git a/src/soc/amd/common/amd_late_init.c b/src/soc/amd/common/amd_late_init.c
new file mode 100644
index 0000000000..d9a5b43743
--- /dev/null
+++ b/src/soc/amd/common/amd_late_init.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+
+static void agesawrapper_post_device(void *unused)
+{
+ if (acpi_is_wakeup_s3())
+ return;
+
+ AGESAWRAPPER(amdinitlate);
+
+ if (!acpi_s3_resume_allowed())
+ return;
+
+ AGESAWRAPPER(amdS3Save);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
+ agesawrapper_post_device, NULL);
diff --git a/src/soc/amd/common/cache_as_ram.inc b/src/soc/amd/common/cache_as_ram.inc
new file mode 100644
index 0000000000..c0a69ec74a
--- /dev/null
+++ b/src/soc/amd/common/cache_as_ram.inc
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/******************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * $Workfile:: cache_as_ram.inc
+ *
+ * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+
+/*
+ * XMM map:
+ * xmm0: BIST
+ * xmm1: backup ebx -- cpu_init_detected
+ */
+
+.code32
+.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+
+cache_as_ram_setup:
+
+ post_code(0xa0)
+
+ /* enable SSE2 128bit instructions */
+ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+
+ movl %cr4, %eax
+ orl $(3<<9), %eax
+ movl %eax, %cr4
+
+ /* Get the cpu_init_detected */
+ mov $1, %eax
+ cpuid
+ shr $24, %ebx
+
+ /* Save the BIST result */
+ cvtsi2sd %ebp, %xmm0
+
+ /* for normal part %ebx already contain cpu_init_detected from fallback call */
+
+ /* Save the cpu_init_detected */
+ cvtsi2sd %ebx, %xmm1
+
+ post_code(0xa1)
+
+ AMD_ENABLE_STACK
+
+ /* Align the stack. */
+ and $0xFFFFFFF0, %esp
+
+#ifdef __x86_64__
+ /* switch to 64 bit long mode */
+ mov %esi, %ecx
+ add $0, %ecx # core number
+ xor %eax, %eax
+ lea (0x1000+0x23)(%ecx), %edi
+ mov %edi, (%ecx)
+ mov %eax, 4(%ecx)
+
+ lea 0x1000(%ecx), %edi
+ movl $0x000000e3, 0x00(%edi)
+ movl %eax, 0x04(%edi)
+ movl $0x400000e3, 0x08(%edi)
+ movl %eax, 0x0c(%edi)
+ movl $0x800000e3, 0x10(%edi)
+ movl %eax, 0x14(%edi)
+ movl $0xc00000e3, 0x18(%edi)
+ movl %eax, 0x1c(%edi)
+
+ # load ROM based identity mapped page tables
+ mov %ecx, %eax
+ mov %eax, %cr3
+
+ # enable PAE
+ mov %cr4, %eax
+ bts $5, %eax
+ mov %eax, %cr4
+
+ # enable long mode
+ mov $0xC0000080, %ecx
+ rdmsr
+ bts $8, %eax
+ wrmsr
+
+ # enable paging
+ mov %cr0, %eax
+ bts $31, %eax
+ mov %eax, %cr0
+
+ # use call far to switch to 64-bit code segment
+ ljmp $0x18, $1f
+1:
+ /* Pass the cpu_init_detected */
+ cvtsd2si %xmm1, %esi
+
+ /* Pass the BIST result */
+ cvtsd2si %xmm0, %edi
+
+
+ .code64
+ call cache_as_ram_main
+ .code32
+
+#else
+
+ /* Restore the BIST result */
+ cvtsd2si %xmm0, %edx
+
+ /* Restore the cpu_init_detected */
+ cvtsd2si %xmm1, %ebx
+
+ /* Must maintain 16-byte stack alignment here. */
+ pushl $0x0
+ pushl $0x0
+ pushl %ebx /* init detected */
+ pushl %edx /* bist */
+ call cache_as_ram_main
+#endif
+
+ /* Should never see this postcode */
+ post_code(0xaf)
+stop:
+ jmp stop
+
+disable_cache_as_ram:
+ /* Save return stack */
+ movd 0(%esp), %xmm1
+ movd %esp, %xmm0
+
+ /* Disable cache */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ AMD_DISABLE_STACK
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
+ xorl %eax, %eax
+
+ /* Restore the return stack */
+ wbinvd
+ movd %xmm0, %esp
+ movd %xmm1, (%esp)
+ ret
+
+cache_as_ram_setup_out:
+#ifdef __x86_64__
+.code64
+#endif
diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c
new file mode 100644
index 0000000000..b733fe881e
--- /dev/null
+++ b/src/soc/amd/common/heapmanager.c
@@ -0,0 +1,319 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <AGESA.h>
+#include <amdlib.h>
+#include <arch/acpi.h>
+#include <BiosCallOuts.h>
+#include <cbmem.h>
+#include <heapManager.h>
+#include <string.h>
+
+UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
+{
+ UINT32 heap = BIOS_HEAP_START_ADDRESS;
+
+ if (acpi_is_wakeup_s3())
+ heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH);
+
+ return heap;
+}
+
+void EmptyHeap(void)
+{
+ void *BiosManagerPtr = (void *) GetHeapBase(NULL);
+ memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
+}
+
+AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof(BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof(BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof(BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof(BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof(BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap.
+ * If it has, return AGESA_BOUNDS_CHK.
+ */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ * to the end of the allocated nodes list.
+ */
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer
+ * size, return AGESA_BOUNDS_CHK.
+ */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ * StartOfFreedNodes to reflect the new free node.
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof(BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ * Return AGESA_BOUNDS_CHK if the BufferHandle is not found.
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof(BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ * Update NextNodeOffset and BufferSize to include the
+ * size of BIOS_BUFFER_NODE.
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ * should be placed.
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ * concatenate both nodes.
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ * concatenate both nodes.
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/spi.c
new file mode 100644
index 0000000000..ce6deef505
--- /dev/null
+++ b/src/soc/amd/common/spi.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
+{
+ struct spi_flash *flash;
+
+ spi_init();
+ flash = spi_flash_probe(0, 0);
+ if (!flash) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ /* Dont make flow stop. */
+ return;
+ }
+
+ spi_flash_volatile_group_begin(flash);
+
+ spi_flash_erase(flash, pos, size);
+ spi_flash_write(flash, pos, sizeof(len), &len);
+ spi_flash_write(flash, pos + sizeof(len), len, buf);
+
+ spi_flash_volatile_group_end(flash);
+
+ return;
+}
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 4cd3116ecd..591037f4ab 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -13,14 +13,61 @@
## GNU General Public License for more details.
##
-config SOC_AMD_STONEYRIDGE
+config SOC_AMD_STONEYRIDGE_FP4
bool
+ help
+ AMD Stoney Ridge FP4 support
+
+config SOC_AMD_STONEYRIDGE_FT4
+ bool
+ help
+ AMD Stoney Ridge FT4 support
+
+if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
+ select LAPIC_MONOTONIC_TIMER
select SOC_AMD_COMMON
+ select SOC_AMD_PI
+ select SPI_FLASH if HAVE_ACPI_RESUME
+ select TSC_SYNC_LFENCE
+ select UDELAY_LAPIC
+
+config UDELAY_LAPIC_FIXED_FSB
+ int
+ default 200
+
+# TODO: Sync these with definitions in PI vendorcode.
+# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
+# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
-if SOC_AMD_STONEYRIDGE
+config DCACHE_RAM_BASE
+ hex
+ default 0x30000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x10000
+
+config CPU_ADDR_BITS
+ int
+ default 48
+
+config CBB
+ hex
+ default 0x0
+
+config CDB
+ hex
+ default 0x18
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
@@ -164,4 +211,4 @@ config STONEYRIDGE_UART
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.
-endif # SOC_AMD_STONEYRIDGE
+endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 7c2682c9bd..9214488fc7 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -27,10 +27,19 @@
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
-ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y)
+ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
+
+subdirs-y += ../../../cpu/amd/mtrr/
+subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/x86/lapic
+subdirs-y += ../../../cpu/x86/cache
+subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/pae
+subdirs-y += ../../../cpu/x86/smm
romstage-y += early_setup.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
+romstage-y += fixme.c
romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
romstage-y += smbus.c
romstage-y += smbus_spd.c
@@ -39,12 +48,14 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
ramstage-y += chip.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+ramstage-y += fixme.c
ramstage-y += gpio.c
ramstage-y += hda.c
ramstage-y += hudson.c
ramstage-y += ide.c
ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
ramstage-y += lpc.c
+ramstage-y += model_15_init.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += reset.c
@@ -233,4 +244,4 @@ apu/amdfw-type := raw
endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
-endif
+endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
new file mode 100644
index 0000000000..aae3287ba6
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Processor Object
+ *
+ */
+Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+} /* End _PR scope */
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
new file mode 100644
index 0000000000..781d0097b0
--- /dev/null
+++ b/src/soc/amd/stoneyridge/fixme.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <amdlib.h>
+
+void amd_initcpuio(void)
+{
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* The platform BIOS needs to ensure the memory ranges of SB800
+ * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
+ * ACPI) are set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
+ /* last address before processor local APIC at FEE00000 */
+ PciData = 0x00FEDF00;
+ PciData |= 1 << 7; /* set NP (non-posted) bit */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
+ /* lowest NP address is HPET at FED00000 */
+ PciData = (0xFED00000 >> 8) | 3;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; /* last address before non-posted range */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+}
+
+void amd_initmmio(void)
+{
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO
+ configuration base Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \
+ (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
+ 0x800ull;
+ LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+
+ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
+ MsrReg |= 1 << 11;
+ LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
+ }
+}
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
new file mode 100644
index 0000000000..02e5b79e84
--- /dev/null
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/acpi.h>
+
+#include <amdlib.h>
+#include <PspBaseLib.h>
+
+void PSPProgBar3Msr(void *Buffer);
+
+void PSPProgBar3Msr(void *Buffer)
+{
+ u32 Bar3Addr;
+ u64 Tmp64;
+ /* Get Bar3 Addr */
+ Bar3Addr = PspLibPciReadPspConfig(0x20);
+ Tmp64 = Bar3Addr;
+ printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
+ LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
+ LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
+}
+
+static void model_15_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Model 15 Init.\n");
+
+ u8 i;
+ msr_t msr;
+ int msrno;
+#if CONFIG_LOGICAL_CPUS
+ u32 siblings;
+#endif
+
+ disable_cache();
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+ // BSP: make a0000-bffff UC, c0000-fffff WB
+ msr.lo = msr.hi = 0;
+ wrmsr(0x259, msr);
+ msr.lo = msr.hi = 0x1e1e1e1e;
+ wrmsr(0x250, msr);
+ wrmsr(0x258, msr);
+ for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr(msrno, msr);
+
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+ x86_mtrr_check();
+ x86_enable_cache();
+
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < 6; i++)
+ wrmsr(MCI_STATUS + (i * 4), msr);
+
+
+ /* Enable the local CPU APICs */
+ setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS
+ siblings = cpuid_ecx(0x80000008) & 0xff;
+
+ if (siblings > 0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1 << (33 - 32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+ PSPProgBar3Msr(NULL);
+
+ /* DisableCf8ExtCfg */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.hi &= ~(1 << (46 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+
+
+ /* Write protect SMM space with SMMLOCK. */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_15_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x670f00 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_15 __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index 978170f00a..89c5a90448 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
+# Copyright (C) 2013-2017 Sage Electronic Engineering, LLC
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -13,13 +13,14 @@
# GNU General Public License for more details.
#
-if CPU_AMD_PI
+if CPU_AMD_PI || SOC_AMD_PI
menu "AMD Platform Initialization"
choice
prompt "AGESA source"
default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI
+ default CPU_AMD_AGESA_BINARY_PI if SOC_AMD_PI
default CPU_AMD_AGESA_OPENSOURCE
help
Select the method for including the AMD Platform Initialization
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index ef317f2dee..971e3b1f89 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -26,7 +26,7 @@
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4 || CPU_AMD_PI_00660F01
+if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
config AGESA_BINARY_PI_VENDORCODE_PATH
string "AGESA PI directory path"
@@ -34,6 +34,8 @@ config AGESA_BINARY_PI_VENDORCODE_PATH
default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01
default "src/vendorcode/amd/pi/00670F00" if CPU_AMD_PI_00670F00_FP4
default "src/vendorcode/amd/pi/00670F00" if CPU_AMD_PI_00670F00_FT4
+ default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4
+ default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4
default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01
help
Specify where to find the AGESA header files
@@ -45,6 +47,8 @@ config AGESA_BINARY_PI_FILE
default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if CPU_AMD_PI_00670F00_FP4
default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if CPU_AMD_PI_00670F00_FT4
+ default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4
+ default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4
default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01
help
Specify the binary file to use for AMD platform initialization.
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 279b89df4a..e686700ee3 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -28,8 +28,9 @@
#
#*****************************************************************************
-ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_CPU_AMD_PI_00660F01),y)
+ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_CPU_AMD_PI_00660F01)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
# AGESA V5 Files
+
AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
AGESA_INC = -I$(obj)
@@ -48,7 +49,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
-ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4),y)
+ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern
AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib
endif
@@ -62,7 +63,7 @@ endif
AGESA_INC += -I$(src)/northbridge/amd/pi
-ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y)
+ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
AGESA_INC += -I$(src)/soc/amd/stoneyridge/include
else
AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
@@ -110,7 +111,7 @@ endef
agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
-ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4),y)
+ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 21:09:34 +0000