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-rw-r--r--src/cpu/qemu-x86/Kconfig1
-rw-r--r--src/cpu/qemu-x86/Makefile.inc2
-rw-r--r--src/cpu/qemu-x86/bootblock.c35
-rw-r--r--src/cpu/qemu-x86/cache_as_ram_bootblock.S (renamed from src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc)55
-rw-r--r--src/mainboard/emulation/qemu-i440fx/Kconfig12
-rw-r--r--src/mainboard/emulation/qemu-i440fx/Makefile.inc1
-rw-r--r--src/mainboard/emulation/qemu-i440fx/romstage.c22
-rw-r--r--src/mainboard/emulation/qemu-q35/Kconfig12
-rw-r--r--src/mainboard/emulation/qemu-q35/Makefile.inc2
-rw-r--r--src/mainboard/emulation/qemu-q35/bootblock.c26
-rw-r--r--src/mainboard/emulation/qemu-q35/romstage.c24
11 files changed, 122 insertions, 70 deletions
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index ab8e1a9919..70cce9b705 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -21,3 +21,4 @@ config CPU_QEMU_X86
select ARCH_RAMSTAGE_X86_32
select SMP
select UDELAY_TSC
+ select C_ENVIRONMENT_BOOTBLOCK
diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc
index 288eea67f5..8ddaa81227 100644
--- a/src/cpu/qemu-x86/Makefile.inc
+++ b/src/cpu/qemu-x86/Makefile.inc
@@ -12,6 +12,8 @@
## GNU General Public License for more details.
##
+bootblock-y += cache_as_ram_bootblock.S
+bootblock-y += bootblock.c
ramstage-y += qemu.c
subdirs-y += ../x86/mtrr
subdirs-y += ../x86/lapic
diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c
new file mode 100644
index 0000000000..fd14c7e0ef
--- /dev/null
+++ b/src/cpu/qemu-x86/bootblock.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist);
+
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+ post_code(0x05);
+
+ /* Halt if there was a built in self test failure */
+ if (bist) {
+ console_init();
+ report_bist_failure(bist);
+ }
+
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_timestamp(base_timestamp, NULL, 0);
+}
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index d36341c78b..8e78aaaf96 100644
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,14 +15,11 @@
* GNU General Public License for more details.
*/
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
- /* Save the BIST result. */
- movl %eax, %ebp
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -31,33 +29,34 @@ cache_as_ram:
*/
post_code(0x21)
- /*
- * Set up the stack pointer, use top of real mode (640k) memory.
- * This value also keeps the copy_and_run stack out of the way
- * of big ramstages. The ramstage will load its own %esp so
- * there is no harm in using this value.
- */
- movl $0xa0000, %eax
- movl %eax, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
+ movl $_car_stack_end, %esp
+ /* Align the stack and keep aligned for call to bootblock_c_entry() */
+ and $0xfffffff0, %esp
+ sub $12, %esp
+
+ /* Clear the cache memory region. This will also clear CAR GLOBAL */
+ movl $_car_region_start, %esi
+ movl %esi, %edi
+ movl $_car_region_end, %ecx
+ sub $_car_region_start, %ecx
+ shr $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* Restore the BIST result and timestamps. */
+ movd %mm0, %ebx
+ movd %mm1, %eax
+ movd %mm2, %edx
+
+ pushl %ebx
+ pushl %edx
pushl %eax
-before_romstage:
+before_c_entry:
post_code(0x29)
- /* Call romstage.c main function. */
- call romstage_main
-
- post_code(0x30)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
-
- call copy_and_run
-
+ call bootblock_c_entry_bist
+ /* Never returns */
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index fc56ab6fa3..2435729ced 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_256
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select BOOTBLOCK_CONSOLE
config MAINBOARD_DIR
string
@@ -25,12 +26,19 @@ config IRQ_SLOT_COUNT
int
default 6
+# Skip the first 64KiB as coreboot table pointer is installed
+# at address 0
config DCACHE_RAM_BASE
hex
- default 0xd0000
+ default 0x10000
+# Memory at 0xa0000 decodes to VGA
config DCACHE_RAM_SIZE
hex
- default 0x10000
+ default 0x90000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x4000
endif # BOARD_EMULATION_QEMU_X86_I440FX
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
index ecc049ea5c..9e2880a6a0 100644
--- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
@@ -1,4 +1,3 @@
-cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += northbridge.c
ramstage-y += fw_cfg.c
romstage-y += memory.c
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index 953062163d..e31394c282 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Stefan Reinauer
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,30 +17,17 @@
#include <stdint.h>
#include <cbmem.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <timestamp.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
+#include <program_loading.h>
-
-void *asmlinkage romstage_main(unsigned long bist)
+asmlinkage void car_stage_entry(void)
{
- int cbmem_was_initted;
-
- /* init_timer(); */
- post_code(0x05);
-
console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- cbmem_was_initted = !cbmem_recovery(0);
+ cbmem_recovery(0);
- timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Emulation uses fixed low stack during ramstage. */
- return NULL;
+ run_ramstage();
}
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 10b5a936c4..4394530fad 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select BOOTBLOCK_CONSOLE
config MAINBOARD_DIR
string
@@ -28,17 +29,24 @@ config MMCONF_BASE_ADDRESS
hex
default 0xb0000000
+# Skip the first 64KiB as coreboot table pointer is installed
+# at address 0
config DCACHE_RAM_BASE
hex
- default 0xd0000
+ default 0x10000
+# Memory at 0xa0000 decodes to VGA
config DCACHE_RAM_SIZE
hex
- default 0x10000
+ default 0x90000
# Do not show IFD/blob options since QEMU doesn't care
config HAVE_INTEL_FIRMWARE
bool
default n
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x4000
+
endif # BOARD_EMULATION_QEMU_X86_Q35
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index 923a28ed34..1503220c9c 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -1,5 +1,5 @@
-cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += ../qemu-i440fx/northbridge.c
ramstage-y += ../qemu-i440fx/memory.c
ramstage-y += ../qemu-i440fx/fw_cfg.c
romstage-y += ../qemu-i440fx/memory.c
+bootblock-y += bootblock.c
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 3625cf903a..2125bd1db3 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -12,6 +12,8 @@
*/
#include <arch/io.h>
+#include <bootblock_common.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
/* Just define these here, there is no gm35.h file to include. */
#define D0F0_PCIEXBAR_LO 0x60
@@ -39,7 +41,29 @@ static void bootblock_northbridge_init(void)
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
}
-static void bootblock_mainboard_init(void)
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ pci_devfn_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void bootblock_southbridge_init(void)
+{
+ enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+ (uintptr_t)DEFAULT_RCBA | 1);
+}
+
+void bootblock_soc_init(void)
{
bootblock_northbridge_init();
bootblock_southbridge_init();
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index deb94af777..2b8d9351c0 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Stefan Reinauer
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,32 +17,19 @@
#include <stdint.h>
#include <cbmem.h>
#include <console/console.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <timestamp.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <program_loading.h>
-void * asmlinkage romstage_main(unsigned long bist)
+asmlinkage void car_stage_entry(void)
{
- int cbmem_was_initted;
-
- /* init_timer(); */
- post_code(0x05);
-
i82801ix_early_init();
console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- cbmem_was_initted = !cbmem_recovery(0);
+ cbmem_recovery(0);
- timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Emulation uses fixed low stack during ramstage. */
- return NULL;
+ run_ramstage();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:01:17 +0000