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-rw-r--r--src/arch/i386/include/arch/acpi.h1
-rw-r--r--src/arch/i386/init/crt0_prologue.inc3
-rw-r--r--src/arch/i386/init/crt0_romcc_epilogue.inc111
-rw-r--r--src/cpu/amd/car/copy_and_run.c4
-rw-r--r--src/cpu/x86/car/copy_and_run.c2
5 files changed, 11 insertions, 110 deletions
diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index 23e4f0d109..c8f9b00217 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -407,7 +407,6 @@ extern u8 acpi_slp_type;
void suspend_resume(void);
void *acpi_find_wakeup_vector(void);
void *acpi_get_wakeup_rsdp(void);
-void acpi_jmp_to_realm_wakeup(u32 linear_addr) __attribute__((regparm(0)));
void acpi_jump_to_wakeup(void *wakeup_addr);
int acpi_get_sleep_type(void);
diff --git a/src/arch/i386/init/crt0_prologue.inc b/src/arch/i386/init/crt0_prologue.inc
index b0ce2cf869..f5d8b6f659 100644
--- a/src/arch/i386/init/crt0_prologue.inc
+++ b/src/arch/i386/init/crt0_prologue.inc
@@ -3,8 +3,7 @@
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * published by the Free Software Foundation; version 2 of the License.
*/
diff --git a/src/arch/i386/init/crt0_romcc_epilogue.inc b/src/arch/i386/init/crt0_romcc_epilogue.inc
index a8a6043830..25c3633c66 100644
--- a/src/arch/i386/init/crt0_romcc_epilogue.inc
+++ b/src/arch/i386/init/crt0_romcc_epilogue.inc
@@ -1,124 +1,27 @@
-/* -*- asm -*-
- * $ $
- *
- */
-
/*
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+ * Copyright 2002 Eric Biederman
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
- *
- * - Converted to gas assembly, and refitted to work with etherboot.
- * Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- * Eric Biederman 26 Sept 2002
+ * published by the Free Software Foundation; version 2 of the License.
*/
-
-#ifndef CONSOLE_DEBUG_TX_STRING
- /* uses: esp, ebx, ax, dx */
-# define __CRT_CONSOLE_TX_STRING(string) \
- mov string, %ebx ; \
- CALLSP(crt_console_tx_string)
-
-# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
-# else
-# define CONSOLE_DEBUG_TX_STRING(string)
-# endif
-#endif
-
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
- CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
-
- /*
- * Copy data into RAM and clear the BSS. Since these segments
- * isn\'t really that big we just copy/clear using bytes, not
- * double words.
- */
- post_code(0x11) /* post 11 */
-
- cld /* clear direction flag */
+ post_code(0x11)
+ cld /* clear direction flag */
- /* copy coreboot from it's initial load location to
- * the location it is compiled to run at.
- * Normally this is copying from FLASH ROM to RAM.
- */
movl %ebp, %esi
+
/* FIXME: look for a proper place for the stack */
movl $0x4000000, %esp
movl %esp, %ebp
pushl %esi
- pushl $str_coreboot_ram_name
- call cbfs_and_run_core
+ call copy_and_run
.Lhlt:
- post_code(0xee) /* post fe */
+ post_code(0xee)
hlt
jmp .Lhlt
-#ifdef __CRT_CONSOLE_TX_STRING
- /* Uses esp, ebx, ax, dx */
-crt_console_tx_string:
- mov (%ebx), %al
- inc %ebx
- cmp $0, %al
- jne 9f
- RETSP
-9:
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3f8
-#endif
-/* Data */
-#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
-
-/* Control */
-#define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
-#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
-#define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
-#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
-#define TTYS0_DLL TTYS0_RBR
-#define TTYS0_DLM TTYS0_IER
-
-/* Status */
-#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
-#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
-#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
-
- mov %al, %ah
-10: mov $TTYS0_LSR, %dx
- inb %dx, %al
- test $0x20, %al
- je 10b
- mov $TTYS0_TBR, %dx
- mov %ah, %al
- outb %al, %dx
-
- jmp crt_console_tx_string
-#endif /* __CRT_CONSOLE_TX_STRING */
-
-#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-.section ".rom.data"
-#if CONFIG_COMPRESS
-str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n"
-#else
-str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
-#endif
-str_pre_main: .string "Jumping to coreboot.\r\n"
-.previous
-
-#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-
-str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX
- .string "/coreboot_ram"
diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index fbe3adef84..0d9317db77 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -19,13 +19,13 @@
void cbfs_and_run_core(const char *filename, unsigned ebp);
-static void copy_and_run(unsigned cpu_reset)
+static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
}
#if CONFIG_AP_CODE_IN_CAR == 1
-static void copy_and_run_ap_code_in_car(unsigned ret_addr)
+static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
}
diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index e09aaff5a4..005df98c79 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -21,7 +21,7 @@
void cbfs_and_run_core(const char *filename, unsigned ebp);
-static void copy_and_run(unsigned cpu_reset)
+static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
{
if (cpu_reset == 1) cpu_reset = -1;
else cpu_reset = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 14:04:07 +0000