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-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index d1c5c82b2e..f05f025e8b 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -77,6 +77,14 @@ chip soc/intel/elkhartlake
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+ # Disable LTR for all PCIe root ports
+ register "PcieRpLtrDisable[0]" = "true"
+ register "PcieRpLtrDisable[1]" = "true"
+ register "PcieRpLtrDisable[2]" = "true"
+ register "PcieRpLtrDisable[3]" = "true"
+ register "PcieRpLtrDisable[4]" = "true"
+ register "PcieRpLtrDisable[5]" = "true"
+
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"