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-rw-r--r--src/soc/intel/broadwell/chip.h22
-rw-r--r--src/soc/intel/broadwell/cpu.c20
2 files changed, 38 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 703c865a8f..77c517d5ec 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -130,6 +130,28 @@ struct soc_intel_broadwell_config {
/* Enable S0iX support */
int s0ix_enable;
+ /*
+ * Minimum voltage for C6/C7 state:
+ * 0x67 = 1.6V (full swing)
+ * ...
+ * 0x79 = 1.7V
+ * ...
+ * 0x83 = 1.8V (no swing)
+ */
+ int vr_cpu_min_vid;
+
+ /*
+ * Set slow VR ramp rate on C-state exit:
+ * 0 = Fast VR ramp rate / 2
+ * 1 = Fast VR ramp rate / 4
+ * 2 = Fast VR ramp rate / 8
+ * 3 = Fast VR ramp rate / 16
+ */
+ int vr_slow_ramp_rate_set;
+
+ /* Enable slow VR ramp rate */
+ int vr_slow_ramp_rate_enable;
+
/* Deep SX enable */
int deep_sx_enable_ac;
int deep_sx_enable_dc;
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index b227e0df97..9073241e30 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -180,6 +180,8 @@ static u32 pcode_mailbox_read(u32 command)
static void initialize_vr_config(void)
{
+ device_t dev = SA_DEV_ROOT;
+ config_t *conf = dev->chip_info;
msr_t msr;
printk(BIOS_DEBUG, "Initializing VR config.\n");
@@ -203,17 +205,27 @@ static void initialize_vr_config(void)
msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
/* Set IOUT_OFFSET to 0. */
msr.hi &= ~0xff;
- /* Set exit ramp rate to fast. */
- msr.hi |= (1 << (50 - 32));
/* Set entry ramp rate to slow. */
msr.hi &= ~(1 << (51 - 32));
/* Enable decay mode on C-state entry. */
msr.hi |= (1 << (52 - 32));
- /* Set the slow ramp rate to be fast ramp rate / 4 */
+ /* Set the slow ramp rate */
msr.hi &= ~(0x3 << (53 - 32));
- msr.hi |= (0x01 << (53 - 32));
+ /* Configure the C-state exit ramp rate. */
+ if (conf->vr_slow_ramp_rate_enable) {
+ /* Configured slow ramp rate. */
+ msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32));
+ /* Set exit ramp rate to slow. */
+ msr.hi &= ~(1 << (50 - 32));
+ } else {
+ /* Fast ramp rate / 4. */
+ msr.hi |= (0x01 << (53 - 32));
+ /* Set exit ramp rate to fast. */
+ msr.hi |= (1 << (50 - 32));
+ }
/* Set MIN_VID (31:24) to allow CPU to have full control. */
msr.lo &= ~0xff000000;
+ msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24;
wrmsr(MSR_VR_MISC_CONFIG, msr);
/* Configure VR_MISC_CONFIG2 MSR. */