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-rw-r--r--src/soc/amd/picasso/psp_verstage/fch.c4
-rw-r--r--src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S4
-rw-r--r--src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h52
3 files changed, 52 insertions, 8 deletions
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c
index 7d0b856545..b813770b4a 100644
--- a/src/soc/amd/picasso/psp_verstage/fch.c
+++ b/src/soc/amd/picasso/psp_verstage/fch.c
@@ -124,13 +124,13 @@ static uint32_t map_fch_devices(void)
bar_map[i].set_bar(bar);
}
- return BL_UAPP_OK;
+ return BL_OK;
}
uint32_t unmap_fch_devices(void)
{
void *bar;
- uint32_t err, rtn = BL_UAPP_OK;
+ uint32_t err, rtn = BL_OK;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(bar_map); ++i) {
diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S
index 88bbf7e98a..15340d58ae 100644
--- a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S
+++ b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S
@@ -72,7 +72,7 @@ ENTRY(_psp_vs_start)
// to main BL using Svc_Exit().
//
ShouldNotBeReached:
- mov r0, #BL_UAPP_ERR_GENERIC // Returned from Main
+ mov r0, #BL_ERR_GENERIC // Returned from Main
svc #0x0 // SVC_EXIT
ENDPROC(_psp_vs_start)
@@ -95,7 +95,7 @@ ENTRY(AllocateStack)
bne ret
svcExit:
- mov r0, #BL_UAPP_ERR_GENERIC
+ mov r0, #BL_ERR_GENERIC
svc #0x0 // SVC_EXIT
ret:
diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h
index ab24750f60..1d5e86ffb1 100644
--- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h
+++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h
@@ -1,6 +1,6 @@
/*****************************************************************************
*
- * Copyright (c) 2019, Advanced Micro Devices, Inc.
+ * Copyright (c) 2020, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,51 @@
#ifndef BL_ERRORCODES_PUBLIC_H
#define BL_ERRORCODES_PUBLIC_H
-#define BL_UAPP_OK 0x00 // General - Success
-#define BL_UAPP_ERR_GENERIC 0x01 // Generic Error Code
+/* Bootloader Return Codes, Error only (0x00 through 0x9F) */
+#define BL_OK 0x00 // General - Success
+#define BL_ERR_GENERIC 0x01 // Generic Error Code
+#define BL_ERR_MEMORY 0x02 // Generic Memory Error
+#define BL_ERR_BUFFER_OVERFLOW 0x03 // Buffer Overflow
+#define BL_ERR_INVALID_PARAMETER 0x04 // Invalid Parameter(s)
+#define BL_ERR_DATA_ALIGNMENT 0x06 // Data Alignment Error
+#define BL_ERR_NULL_PTR 0x07 // Null Pointer Error
+#define BL_ERR_INVALID_ADDRESS 0x0A // Invalid Address
+#define BL_ERR_OUT_OF_RESOURCES 0x0B // Out of Resource Error
+#define BL_ERR_DATA_ABORT 0x0D // Data Abort exception
+#define BL_ERR_PREFETCH_ABORT 0x0E // Prefetch Abort exception
+#define BL_ERR_GET_FW_HEADER 0x13 // Failure in retrieving firmware
+ // header
+#define BL_ERR_KEY_SIZE 0x14 // Key size not supported
+#define BL_ERR_ENTRY_NOT_FOUND 0x15 // Entry not found at requested
+ // location
+#define BL_ERR_UNSUPPORTED_PLATFORM 0x16 // Error when feature is not enabled
+ // on a given platform.
+#define BL_ERR_FWVALIDATION 0x18 // Generic FW Validation error
+#define BL_ERR_CCP_RSA 0x19 // RSA operation fail - bootloader
+#define BL_ERR_CCP_PASSTHR 0x1A // CCP Passthrough operation failed
+#define BL_ERR_CCP_AES 0x1B // AES operation failed
+#define BL_ERR_SHA 0x1E // SHA256/SHA384 operation failed
+#define BL_ERR_ZLIB 0x1F // ZLib Decompression operation fail
+#define BL_ERR_DIR_ENTRY_NOT_FOUND 0x22 // PSP directory entry not found
+#define BL_ERR_SYSHUBMAP_FAILED 0x3A // Unable to map a SYSHUB address to
+ // AXI space
+#define BL_ERR_UAPP_PSP_HEADER_NOT_MATCH 0x7A // PSP level directory from OEM user-
+ // app does not match expected value.
+#define BL_ERR_UAPP_BIOS_HEADER_NOT_MATCH 0x7B // BIOS level directory from OEM
+ // user-app not match expected value.
+#define BL_ERR_UAPP_PSP_DIR_OFFSET_NOT_SET 0x7C // PSP Directory offset is not set
+ // by OEM user-app.
+#define BL_ERR_UAPP_BIOS_DIR_OFFSET_NOT_SET 0x7D // BIOS Directory offset is not set
+ // by OEM user-app.
+#define BL_ERR_POSTCODE_MAX_VALUE 0x9F // The maximum allowable error post
-#endif // BL_ERRORCODES_PUBLIC_H
+/* Bootloader Return Codes, Success only (0xA0 through 0xFF) */
+#define BL_SUCCESS_USERMODE_OEM_APP 0xF7 // Updated only PSPFW Status when OEM
+ // PSP BL user app returns success.
+#define BL_SUCCESS_PSP_BIOS_DIRECTORY_UPDATE 0xF8 // PSP and BIOS directories are loaded
+ // into SRAM from the offset provided
+ // by OEM user app.
+
+#define BL_SUCCESS_LAST_CODE 0xFF // Bootloader sequence finished
+
+#endif /* BL_ERRORCODES_PUBLIC_H */