diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/graphics/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 136 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/graphics.h | 54 |
4 files changed, 195 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig new file mode 100644 index 0000000000..4ab92001c3 --- /dev/null +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_GRAPHICS + bool + help + Intel Processor common Graphics support diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc new file mode 100644 index 0000000000..44dfc7ef2c --- /dev/null +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c new file mode 100644 index 0000000000..544ae96231 --- /dev/null +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/graphics.h> +#include <soc/pci_devs.h> + +/* SoC Overrides */ +__attribute__((weak)) void graphics_soc_init(struct device *dev) +{ + /* + * User needs to implement SoC override incase wishes + * to perform certain specific graphics initialization + * along with pci_dev_init(dev) + */ + pci_dev_init(dev); +} + +static uintptr_t graphics_get_bar(unsigned long index) +{ + struct device *dev = SA_DEV_IGD; + struct resource *gm_res; + + /* Check if Graphics PCI device is disabled */ + if (!dev->enabled) + return 0; + + gm_res = find_resource(dev, index); + if (!gm_res) + return 0; + + return gm_res->base; +} + +uintptr_t graphics_get_memory_base(void) +{ + /* + * GFX PCI config space offset 0x18 know as Graphics + * Memory Range Address (GMADR) + */ + uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2); + if (!memory_base) + die("GMADR is not programmed!"); + + return memory_base; +} + +static uintptr_t graphics_get_gtt_base(void) +{ + /* + * GFX PCI config space offset 0x10 know as Graphics + * Translation Table Memory Mapped Range Address + * (GTTMMADR) + */ + static uintptr_t gtt_base; + if (!gtt_base) { + gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0); + if (!gtt_base) + die("GTTMMADR is not programmed!"); + } + return gtt_base; +} + +uint32_t graphics_gtt_read(unsigned long reg) +{ + return read32((void *)(graphics_get_gtt_base() + reg)); +} + +void graphics_gtt_write(unsigned long reg, uint32_t data) +{ + write32((void *)(graphics_get_gtt_base() + reg), data); +} + +void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) +{ + uint32_t val = graphics_gtt_read(reg); + val &= andmask; + val |= ormask; + graphics_gtt_write(reg, val); +} + +static const struct device_operations graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = graphics_soc_init, + .write_acpi_tables = graphics_soc_write_acpi_opregion, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, + PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, + PCI_DEVICE_ID_INTEL_GLK_IGD, + PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, + PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, + PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, + PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, + 0, +}; + +static const struct pci_driver graphics_driver __pci_driver = { + .ops = &graphics_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h new file mode 100644 index 0000000000..f489e27a7b --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H +#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H + +#include <device/device.h> + +/* + * SoC overrides + * + * All new SoC must implement below functionality. + */ + +/* + * Perform Graphics Initialization in ramstage + * Input: + * struct device *dev: device structure + */ +void graphics_soc_init(struct device *dev); + +/* + * Write ASL entry for Graphics opregion + * Input: + * device_t device: device structure + * current: start address of graphics opregion + * rsdp: pointer to RSDT (and XSDT) structure + * + * Output: + * End address of graphics opregion so that the called + * can use the same for future calls to write_acpi_tables + */ +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, + uintptr_t current, struct acpi_rsdp *rsdp); + +/* Graphics MMIO register read/write APIs */ +uint32_t graphics_gtt_read(unsigned long reg); +void graphics_gtt_write(unsigned long reg, uint32_t data); +void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); +uintptr_t graphics_get_memory_base(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ |