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-rw-r--r--src/northbridge/intel/x4x/dq_dqs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 82dca44f72..4722dfe7a6 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -746,7 +746,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
* DDR3 uses flyby topology where the clock signal takes a different path
* than the data signal, to allow for better signal intergrity.
* Therefore the delay on the data signals needs to account for this.
- * This is done by by sampleling the the DQS write (tx) signal back over
+ * This is done by sampleling the DQS write (tx) signal back over
* the DQ signal and looking for delay values where the sample transitions
* from high to low.
* Here the following is done: