4 files changed, 9 insertions, 13 deletions

diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
index 5c0707f8fe..ad796cd556 100644
--- a/src/mainboard/intel/bakersport_fsp/Kconfig
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select OVERRIDE_MRC_CACHE_LOC
 	select POST_IO
-	select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index 2c6239061d..14c9e60b3e 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select OVERRIDE_MRC_CACHE_LOC
 	select POST_IO
-	select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 639071a3c8..87839c40b4 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -47,8 +47,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_CONSTANT_RATE
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
-	select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD
-	select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD
+	select SUPPORT_CPU_UCODE_IN_CBFS
 	select ROMSTAGE_RTC_INIT
 
 config BOOTBLOCK_CPU_INIT
@@ -84,15 +83,6 @@ config VGA_BIOS_ID
 	  This is the default PCI ID for the Bay Trail graphics
 	  devices.  This string names the vbios ROM in cbfs.
 
-config INCLUDE_MICROCODE_IN_BUILD
-	bool "Build in microcode patch"
-	default n
-	help
-	  Enable if the microcode patch is available.  For the
-	  BayTrail - I processors, the filename should start with
-	  "M01".  Using a microcode patch for the incorrect BayTrail
-	  SKU will lead to unpredictable results.
-
 config MICROCODE_INCLUDE_PATH
 	string "Microcode Include path"
 	default "../intel/cpu/baytrail/microcode"
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
index 709ff92f76..57aae34349 100644
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
@@ -19,11 +19,19 @@
 
 unsigned microcode[] = {
 
+/*
+ * The problem is that these microcode files are not in the tree. They come
+ * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
+ * is enabled.
+ */
+#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
+
 /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
 #include "M0230672228.h"  // M0230672: Baytrail "Super SKU" B0/B1
 #include "M0130673322.h"  // M0130673: Baytrail I B2 / B3
 #include "M0130679901.h"  // M0130679: Baytrail I D0
 
+#endif
 	/*  Dummy terminator  */
 	0x0, 0x0, 0x0, 0x0,
 	0x0, 0x0, 0x0, 0x0,