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-rw-r--r--src/cpu/intel/fsp_model_406dx/Kconfig18
-rw-r--r--src/cpu/intel/fsp_model_406dx/Makefile.inc3
-rw-r--r--src/cpu/intel/fsp_model_406dx/model_406dx_init.c3
3 files changed, 9 insertions, 15 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index c36851d485..edf18f5d3e 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -33,6 +33,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
+ # Microcode header files are delivered in FSP package
+ select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
+
choice
prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0
@@ -53,16 +56,9 @@ config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
-config HAVE_CPU_MICROCODE_FILE
- bool "Add microcode file"
- help
- The microcode binary
-
-config CPU_MICROCODE_FILE
- string "Path and filename of CPU microcode"
- default "microcode.bin"
- depends on HAVE_CPU_MICROCODE_FILE
- help
- The path and filename of the file containing the CPU microcode.
+#set up microcode for rangeley POSTGOLD4 release
+config CPU_MICROCODE_HEADER_FILES
+ string
+ default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"
endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 91c7d96aa4..3e293480c2 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -23,6 +23,3 @@ cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
endif
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-# We don't have microcode for this CPU
-# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
-# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 5482e74b7a..17c46b3086 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -170,7 +170,8 @@ static void model_406dx_init(struct device *cpu)
x86_enable_cache();
/* Load microcode */
- intel_update_microcode_from_cbfs();
+ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
configure_mca();