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-rw-r--r--src/mainboard/google/reef/devicetree.cb3
-rw-r--r--src/mainboard/google/reef/gpio.h3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index 5e68d3720c..ea3b20f2e2 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -43,6 +43,9 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+ # Enable I2C2 bus early for TPM access
+ register "i2c[2].early_init" = "1"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 5eb1d1dc29..4230c62ef7 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -344,6 +344,9 @@ static const struct pad_config gpio_table[] = {
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */
+ /* I2C2 - TPM */
+ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
+ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
};
/*