2 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index 9d7fe98dde..68825a365f 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -65,8 +65,38 @@ static void get_microcode_info(const void **microcode, int *parallel)
 	*parallel = 1;
 }
 
+static int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Bits 34:33 indicate how many levels are supported. */
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option. */
+	if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio. */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info Bits 15:8 give max ratio. */
+		msr = rdmsr(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	wrmsr(IA32_PERF_CTL, perf_ctl);
+}
+
 static void post_mp_init(void)
 {
+	/* Set Max Ratio */
+	set_max_ratio();
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	   start flowing. */
 	southbridge_smm_enable_smi();
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f5ea34ccd3..6b87061109 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,10 +21,12 @@
 #define MSR_IA32_PLATFORM_ID	0x17
 #define MSR_CORE_THREAD_COUNT	0x35
 #define MSR_PLATFORM_INFO	0xce
+#define IA32_PERF_CTL		0x199
 #define MSR_TURBO_RATIO_LIMIT	0x1ad
 #define MSR_IA32_MC0_STATUS	0x400
 #define MSR_PKG_POWER_SKU_UNIT	0x606
 #define MSR_PKG_POWER_LIMIT	0x610
+#define MSR_CONFIG_TDP_NOMINAL	0x648
 
 #define SMM_MCA_CAP_MSR		0x17d
 #define  SMM_CPU_SVRSTR_BIT	57