2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h
index aa9c8bbca9..1eab709462 100644
--- a/src/soc/mediatek/mt8173/include/soc/pll.h
+++ b/src/soc/mediatek/mt8173/include/soc/pll.h
@@ -284,5 +284,6 @@ enum {
 void mt_pll_post_init(void);
 void mt_pll_init(void);
 void mt_pll_set_aud_div(u32 rate);
+void mt_pll_enable_ssusb_clk(void);
 
 #endif /* SOC_MEDIATEK_MT8173_PLL_H */
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 4f386c0a32..3faf7859a7 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -443,6 +443,23 @@ void mt_pll_init(void)
 		(1 << 4) | (1 << 2) | (1 << 0));
 }
 
+/* Turn on ADA_SSUSB_XTAL_CK 26MHz */
+void mt_pll_enable_ssusb_clk(void)
+{
+	/* set  RG_LTECLKSQ_EN */
+	setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1);
+	udelay(100); /* wait for PLL stable */
+
+	/* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */
+	setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1);
+	setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1);
+	udelay(100); /* wait for PLL stable */
+
+	/* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */
+	setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));
+}
+
+
 /* after pmic_init */
 void mt_pll_post_init(void)
 {