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-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 6ed3dcd2de..9c105cadc2 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -102,6 +102,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
+ /* Image clock: disable all clocks for bypassing FSP pin mux */
+ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
+
/* Enable Hyper Threading */
m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */