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-rw-r--r--src/mainboard/intel/galileo/gen1.h50
-rw-r--r--src/mainboard/intel/galileo/gen2.h22
-rw-r--r--src/mainboard/intel/galileo/gpio.c38
-rw-r--r--src/soc/intel/quark/Kconfig27
-rw-r--r--src/soc/intel/quark/include/soc/pci_devs.h3
-rw-r--r--src/soc/intel/quark/include/soc/reg_access.h1
-rw-r--r--src/soc/intel/quark/romstage/romstage.c12
7 files changed, 126 insertions, 27 deletions
diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h
index e1e8f59070..23b23091d2 100644
--- a/src/mainboard/intel/galileo/gen1.h
+++ b/src/mainboard/intel/galileo/gen1.h
@@ -59,6 +59,56 @@ static const struct reg_script gen1_gpio_init[] = {
REG_SCRIPT_END
};
+static const struct reg_script gen1_hsuart0_0x20[] = {
+ /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
+ * Set IO1_MUX (EXP.PORT3_5) output, low
+ * Set LVL_OE (GPIO_SUS2) output, high
+ */
+
+ REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
+
+ /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
+ * Set IO0_MUX (EXP.PORT3_4) output, low
+ * Set LVL_OE (GPIO_SUS2) output, high
+ */
+ REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
+
+ REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
+ REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
+ REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
+
+ REG_SCRIPT_END
+};
+
+static const struct reg_script gen1_hsuart0_0x21[] = {
+ /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
+ * Set IO1_MUX (EXP.PORT3_5) output, low
+ * Set LVL_OE (GPIO_SUS2) output, high
+ */
+
+ REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
+
+ /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
+ * Set IO0_MUX (EXP.PORT3_4) output, low
+ * Set LVL_OE (GPIO_SUS2) output, high
+ */
+ REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
+ REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
+
+ REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
+ REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
+ REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
+
+ REG_SCRIPT_END
+};
+
static const struct reg_script gen1_i2c_0x20_init[] = {
/* Route I2C pins to Arduino header:
* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h
index 8eee744392..10c832198e 100644
--- a/src/mainboard/intel/galileo/gen2.h
+++ b/src/mainboard/intel/galileo/gen2.h
@@ -52,6 +52,28 @@ static const struct reg_script gen2_gpio_init[] = {
REG_SCRIPT_END
};
+static const struct reg_script gen2_hsuart0[] = {
+ /* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1
+ * Set MUX7_SEL (EXP1.P1_5) high
+ * Configure MUX7_SEL (EXP1.P1_5) as an output
+ * Set LVL_B_OE6_N (EXP0.P1_4) low
+ * Configure LVL_B_OE6_N (EXP0.P1_4) as an output
+ */
+ REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5),
+ REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5),
+ REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
+ REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
+
+ /* Route DIGITAL 0 -> IO0 -> UART0_RXD
+ * Set LVL_C_OE0_N (EXP1.P0_0) high
+ * Configure LVL_C_OE0_N (EXP1.P0_0) as an output
+ */
+ REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0),
+ REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0),
+
+ REG_SCRIPT_END
+};
+
static const struct reg_script gen2_i2c_init[] = {
/* Route I2C to Arduino Shield connector:
* Set AMUX1_IN (EXP2.P1_4) low
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index 31843814c2..0b55bc6ae2 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -15,11 +15,35 @@
#include <arch/io.h>
#include <console/console.h>
+#include <fsp/romstage.h>
#include <soc/ramstage.h>
#include "reg_access.h"
#include "gen1.h"
#include "gen2.h"
+void car_mainboard_pre_console_init(void)
+{
+ const struct reg_script *script;
+
+ /* Initialize the GPIO controllers */
+ if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ script = gen2_gpio_init;
+ else
+ script = gen1_gpio_init;
+ reg_script_run(script);
+
+ /* Initialize the RXD and TXD paths for UART0 */
+ if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
+ if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ script = gen2_hsuart0;
+ else
+ script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
+ & GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
+ ? gen1_hsuart0_0x21 : gen1_hsuart0_0x20;
+ reg_script_run(script);
+ }
+}
+
void mainboard_gpio_i2c_init(device_t dev)
{
const struct reg_script *script;
@@ -33,24 +57,12 @@ void mainboard_gpio_i2c_init(device_t dev)
/* Determine which I2C address is in use */
script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
- ? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
+ ? gen1_i2c_0x21_init : gen1_i2c_0x20_init;
/* Initialize the I2C chips */
reg_script_run(script);
}
-void mainboard_gpio_init(void)
-{
- const struct reg_script *script;
-
- /* Initialize the GPIO controllers */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
- script = gen2_gpio_init;
- else
- script = gen1_gpio_init;
- reg_script_run(script);
-}
-
void mainboard_gpio_pcie_reset(uint32_t pin_value)
{
uint32_t pin_number;
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 6a2349fb8d..2c7ec641b6 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -40,9 +40,19 @@ config CPU_SPECIFIC_OPTIONS
# The following options configure the debug serial port
#####
+config ENABLE_BUILTIN_HSUART0
+ bool "Enable built-in HSUART0"
+ default n
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
+ help
+ The Quark SoC has two HSUART. Choose this option to configure the pads
+ and enable HSUART0, which can be used for the debug console.
+
config ENABLE_BUILTIN_HSUART1
bool "Enable built-in HSUART1"
- default y
+ default n
+ depends on ! ENABLE_BUILTIN_HSUART0
select NO_UART_ON_SUPERIO
select DRIVERS_UART_8250MEM_32
help
@@ -50,23 +60,24 @@ config ENABLE_BUILTIN_HSUART1
and enable HSUART1, which can be used for the debug console.
config TTYS0_BASE
- hex "HSUART1 Base Address"
- depends on ENABLE_BUILTIN_HSUART1
+ hex "HSUART Base Address"
default 0xA0019000
+ depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
help
- Memory mapped MMIO of HSUART1.
+ Memory mapped MMIO of HSUART.
config TTYS0_LCS
int
- depends on ENABLE_BUILTIN_HSUART1
default 3
+ depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
-# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12
+# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
# Valid bit, PCI UART in use: 1 << 31
config UART_PCI_ADDR
hex
- depends on ENABLE_BUILTIN_HSUART1
- default 0x800a5000
+ default 0x800a1000 if ENABLE_BUILTIN_HSUART0
+ default 0x800a5000 if ENABLE_BUILTIN_HSUART1
+ depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
#####
# Debug support
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 278a012d11..0c99eb9de4 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -33,11 +33,14 @@
/* IO Fabric 1 */
#define SIO1_DEV 0x14
+#define HSUART0_DEV SIO1_DEV
#define HSUART1_DEV SIO1_DEV
+#define HSUART0_FUNC 1
#define USB_DEV_PORT_FUNC 2
#define EHCI_FUNC 3
#define OHCI_FUNC 4
#define HSUART1_FUNC 5
+#define HSUART0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC)
#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC)
/* IO Fabric 2 */
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index e7a8963b8c..b934032358 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -203,7 +203,6 @@ enum {
REG_USB_RXW(reg_, 0xffffffff, value_)
void *get_i2c_address(void);
-void mainboard_gpio_init(void);
void mainboard_gpio_pcie_reset(uint32_t pin_value);
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 5be022a8d6..e27aa685be 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -67,6 +67,13 @@ static const struct reg_script hsuart_init[] = {
void car_soc_pre_console_init(void)
{
+ /* Initialize the controllers */
+ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
+ reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
+
+ /* Enable the HSUART */
+ if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
+ reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
}
@@ -74,11 +81,6 @@ void car_soc_pre_console_init(void)
void car_soc_post_console_init(void)
{
report_platform_info();
-
- /* Initialize the controllers */
- reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
- reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
- mainboard_gpio_init();
};
static struct chipset_power_state power_state CAR_GLOBAL;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 13:55:56 +0000