summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/bootblock/bootblock.c43
-rw-r--r--src/soc/intel/cannonlake/include/soc/bootblock.h31
-rw-r--r--src/soc/intel/cannonlake/include/soc/iomap.h79
3 files changed, 153 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
new file mode 100644
index 0000000000..293a104158
--- /dev/null
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation..
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <intelblocks/gspi.h>
+#include <soc/bootblock.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_timestamp(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_systemagent_early_init();
+ bootblock_pch_early_init();
+ bootblock_cpu_init();
+ pch_early_iorange_init();
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))
+ pch_uart_init();
+}
+
+void bootblock_soc_init(void)
+{
+ report_platform_info();
+ set_max_freq();
+ pch_early_init();
+}
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h
new file mode 100644
index 0000000000..eb4c9b0e42
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_
+#define _SOC_CANNONLAKE_BOOTBLOCK_H_
+
+#include <intelblocks/systemagent.h>
+
+/* Bootblock pre console init programing */
+void bootblock_cpu_init(void);
+void bootblock_pch_early_init(void);
+
+/* Bootblock post console init programing */
+void pch_early_init(void);
+void pch_early_iorange_init(void);
+void report_platform_info(void);
+void set_max_freq(void);
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
new file mode 100644
index 0000000000..c2bb0500db
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_IOMAP_H_
+#define _SOC_CANNONLAKE_IOMAP_H_
+
+/*
+ * Memory-mapped I/O registers.
+ */
+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE 0x4000000
+
+#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
+#define PCH_PRESERVED_BASE_SIZE 0x02000000
+
+#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
+#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
+#define UART_DEBUG_BASE_ADDRESS 0xfe036000
+#define UART_DEBUG_BASE_SIZE 0x1000
+
+#define EARLY_I2C_BASE_ADDRESS 0xfe040000
+#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+
+#define MCH_BASE_ADDRESS 0xfed10000
+#define MCH_BASE_SIZE 0x8000
+
+#define DMI_BASE_ADDRESS 0xfeda0000
+#define DMI_BASE_SIZE 0x1000
+
+#define EP_BASE_ADDRESS 0xfeda1000
+#define EP_BASE_SIZE 0x1000
+
+#define EDRAM_BASE_ADDRESS 0xfed80000
+#define EDRAM_BASE_SIZE 0x4000
+
+#define REG_BASE_ADDRESS 0xfc000000
+#define REG_BASE_SIZE 0x1000
+
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#define PCH_PWRM_BASE_ADDRESS 0xfe000000
+#define PCH_PWRM_BASE_SIZE 0x10000
+
+#define SPI_BASE_ADDRESS 0xfe010000
+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
+
+#define GPIO_BASE_SIZE 0x10000
+
+#define HECI1_BASE_ADDRESS 0xFEDA2000
+
+/* CPU Trace reserved memory size */
+#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
+
+/*
+ * I/O port address space
+ */
+#define SMBUS_BASE_ADDRESS 0x0efa0
+#define SMBUS_BASE_SIZE 0x20
+
+#define ACPI_BASE_ADDRESS 0x1800
+#define ACPI_BASE_SIZE 0x100
+
+#define TCO_BASE_ADDRESS 0x400
+#define TCO_BASE_SIZE 0x20
+
+#endif