summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/arch/ppc/include/ppc4xx.h11
-rwxr-xr-xsrc/arch/ppc/include/ppc74xx.h32
-rwxr-xr-xsrc/arch/ppc/include/ppc750.h33
-rw-r--r--src/arch/ppc/include/ppc970.h30
-rw-r--r--src/arch/ppc/include/ppcreg.h86
-rw-r--r--src/cpu/ppc/mpc74xx/mpc74xx.inc2
-rw-r--r--src/cpu/ppc/ppc7xx/ppc7xx.inc2
-rw-r--r--src/cpu/ppc/ppc970/ppc970.inc86
-rw-r--r--src/mainboard/momentum/apache/Options.lb1
9 files changed, 179 insertions, 104 deletions
diff --git a/src/arch/ppc/include/ppc4xx.h b/src/arch/ppc/include/ppc4xx.h
index 279e1aa161..48066cedc2 100644
--- a/src/arch/ppc/include/ppc4xx.h
+++ b/src/arch/ppc/include/ppc4xx.h
@@ -68,6 +68,17 @@
#define sprg6w 0x116 /* Special purpose general 6 - write only */
#define sprg7w 0x117 /* Special purpose general 7 - write only */
+/*----------------------------------------------------------------------------+
+| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
++----------------------------------------------------------------------------*/
+#define MSR_APE 0x00080000 /* wait state enable */
+#define MSR_WE 0x00040000 /* wait state enable */
+#define MSR_CE 0x00020000 /* critical interrupt enable */
+#define MSR_DWE 0x00000400 /* debug wait enable */
+#define MSR_DE 0x00000200 /* debug interrupt enable */
+#define MSR_IR 0x00000020 /* instruction relocale */
+#define MSR_DR 0x00000010 /* data relocale */
+
/******************************************************************************
* Special for PPC405GP
******************************************************************************/
diff --git a/src/arch/ppc/include/ppc74xx.h b/src/arch/ppc/include/ppc74xx.h
new file mode 100755
index 0000000000..121efbe28d
--- /dev/null
+++ b/src/arch/ppc/include/ppc74xx.h
@@ -0,0 +1,32 @@
+/* We are interested in the following hid0 bits:
+ 6 - ECLK - Enable external test clock (603 only)
+ 11 - DPM - Turn on dynamic power management (603 only)
+ 15 - NHR - Not hard reset
+ 16 - ICE - Instruction cache enable
+ 17 - DCE - Data cache enable
+ 18 - ILOCK - Instruction cache lock
+ 19 - DLOCK - Data cache lock
+ 20 - ICFI - Instruction cache invalidate
+ 21 - DCFI - Data cache invalidate
+ 24 - NOSER - Serial execution disable (604 only - turbo mode)
+ 24 - SGE - Store gathering enable (7410 only)
+ 29 - BHT - Branch history table (604 only)
+
+ I made up the tags for the 604 specific bits, as they aren't
+ named in the 604 book. The 603 book calls the invalidate bits
+ ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
+ one, and Motorola named the other. */
+
+#define HID0_ECLK 0x02000000
+#define HID0_DPM 0x00100000
+#define HID0_NHR 0x00010000
+#define HID0_ICE 0x00008000
+#define HID0_DCE 0x00004000
+#define HID0_ILOCK 0x00002000
+#define HID0_DLOCK 0x00001000
+#define HID0_ICFI 0x00000800
+#define HID0_DCFI 0x00000400
+#define HID0_NOSER 0x00000080
+#define HID0_SGE 0x00000080
+#define HID0_BTIC 0x00000020
+#define HID0_BHT 0x00000004
diff --git a/src/arch/ppc/include/ppc750.h b/src/arch/ppc/include/ppc750.h
new file mode 100755
index 0000000000..05fa37e894
--- /dev/null
+++ b/src/arch/ppc/include/ppc750.h
@@ -0,0 +1,33 @@
+/* We are interested in the following hid0 bits:
+ 6 - ECLK - Enable external test clock (603 only)
+ 11 - DPM - Turn on dynamic power management (603 only)
+ 15 - NHR - Not hard reset
+ 16 - ICE - Instruction cache enable
+ 17 - DCE - Data cache enable
+ 18 - ILOCK - Instruction cache lock
+ 19 - DLOCK - Data cache lock
+ 20 - ICFI - Instruction cache invalidate
+ 21 - DCFI - Data cache invalidate
+ 24 - NOSER - Serial execution disable (604 only - turbo mode)
+ 24 - SGE - Store gathering enable (7410 only)
+ 29 - BHT - Branch history table (604 only)
+
+ I made up the tags for the 604 specific bits, as they aren't
+ named in the 604 book. The 603 book calls the invalidate bits
+ ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
+ one, and Motorola named the other. */
+
+#define HID0_ECLK 0x02000000
+#define HID0_DPM 0x00100000
+#define HID0_NHR 0x00010000
+#define HID0_ICE 0x00008000
+#define HID0_DCE 0x00004000
+#define HID0_ILOCK 0x00002000
+#define HID0_DLOCK 0x00001000
+#define HID0_ICFI 0x00000800
+#define HID0_DCFI 0x00000400
+#define HID0_NOSER 0x00000080
+#define HID0_SGE 0x00000080
+#define HID0_BTIC 0x00000020
+#define HID0_BHT 0x00000004
+
diff --git a/src/arch/ppc/include/ppc970.h b/src/arch/ppc/include/ppc970.h
index 7358d52e44..5c0f884972 100644
--- a/src/arch/ppc/include/ppc970.h
+++ b/src/arch/ppc/include/ppc970.h
@@ -18,16 +18,30 @@
| 13-Oct-03 Created MPT
+----------------------------------------------------------------------------*/
-#ifndef _sys_as_archppc970_h_
-#define _sys_as_archppc970_h_
+#ifndef _PPC970_H_
+#define _PPC970_H_
/*----------------------------------------------------------------------------+
-| PVR value.
+| When timers are running based on CPU speed this is the timer to CPU frequency
+| ratio.
+----------------------------------------------------------------------------*/
-#define PVR_970_DD1 0x00391100
-#define PVR_970FX_DD2 0x003C0200
-#define PVR_970FX_DD2_1 0x003C0201
-#define PVR_970FX_DD3 0x003C0300
+#define PPC970_TB_RATIO 8
+
+/*----------------------------------------------------------------------------+
+| Cache line size.
++----------------------------------------------------------------------------*/
+#define CACHE_LINE_SIZE_L1 128
+#define CACHE_LINE_SIZE_L2 128
+
+/*----------------------------------------------------------------------------+
+| SLB size.
++----------------------------------------------------------------------------*/
+#define SLB_SIZE 64
+
+/*----------------------------------------------------------------------------+
+| TLB size.
++----------------------------------------------------------------------------*/
+#define TLB_SIZE 1024
/*----------------------------------------------------------------------------+
| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)
@@ -225,4 +239,4 @@
#define SRR1_ITLB_RELOA 0x00000000000C0000
#define SRR1_RI 0x0000000000000002
-#endif /* _sys_as_archppc970_h_ */
+#endif /* _PPC970_H_ */
diff --git a/src/arch/ppc/include/ppcreg.h b/src/arch/ppc/include/ppcreg.h
index a778a49377..e6bb752b6d 100644
--- a/src/arch/ppc/include/ppcreg.h
+++ b/src/arch/ppc/include/ppcreg.h
@@ -2,78 +2,25 @@
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
/* In the MSR, not all bits are interesting to us
- 13 - POW - Power management
- 14 - TGPR - temporary registers for page table routines
- 15 - ILE - Exception little endian
16 - EE - External interrupts
17 - PR - Privilege level
18 - FP - Floating Point available
19 - ME - Machine check exception enable
20 - FE0 - Floating exception mode 0
- 21 - SE - Single step trace mode
- 22 - BE - Branch trace enable
23 - FE1 - Floating exception mode 1
- 25 - IP - Exception prefix
- 26 - IR - Instruction address translation
- 27 - DR - Data address translation
- 30 - RI - Recoverable exception
- 31 - LE - Little endian mode
MSR_MASK is the bits we do not change.
*/
#define MSR_MASK 0xfff8008c
-#define MSR_POW 0x00040000
-#define MSR_TGPR 0x00020000
-#define MSR_ILE 0x00010000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_FP 0x00002000
#define MSR_ME 0x00001000
#define MSR_FE0 0x00000800
-#define MSR_SE 0x00000400
-#define MSR_BE 0x00000200
#define MSR_FE1 0x00000100
-#define MSR_IP 0x00000040
-#define MSR_IR 0x00000020
-#define MSR_DR 0x00000010
-#define MSR_RI 0x00000002
-#define MSR_LE 0x00000001
#define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
-/* We are interested in the following hid0 bits:
- 6 - ECLK - Enable external test clock (603 only)
- 11 - DPM - Turn on dynamic power management (603 only)
- 15 - NHR - Not hard reset
- 16 - ICE - Instruction cache enable
- 17 - DCE - Data cache enable
- 18 - ILOCK - Instruction cache lock
- 19 - DLOCK - Data cache lock
- 20 - ICFI - Instruction cache invalidate
- 21 - DCFI - Data cache invalidate
- 24 - NOSER - Serial execution disable (604 only - turbo mode)
- 24 - SGE - Store gathering enable (7410 only)
- 29 - BHT - Branch history table (604 only)
-
- I made up the tags for the 604 specific bits, as they aren't
- named in the 604 book. The 603 book calls the invalidate bits
- ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
- one, and Motorola named the other. */
-
-#define HID0_ECLK 0x02000000
-#define HID0_DPM 0x00100000
-#define HID0_NHR 0x00010000
-#define HID0_ICE 0x00008000
-#define HID0_DCE 0x00004000
-#define HID0_ILOCK 0x00002000
-#define HID0_DLOCK 0x00001000
-#define HID0_ICFI 0x00000800
-#define HID0_DCFI 0x00000400
-#define HID0_NOSER 0x00000080
-#define HID0_SGE 0x00000080
-#define HID0_BTIC 0x00000020
-#define HID0_BHT 0x00000004
-
/*
* BAT defines
*/
@@ -181,6 +128,39 @@
#define PVR_8240 0x00810100
#define PVR_8260 PVR_8240
+/*----------------------------------------------------------------------------+
+| Processor Version Register (PVR) values
++----------------------------------------------------------------------------*/
+#define PVR_970 0x0039 /* 970 any revision*/
+#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */
+#define PVR_970FX 0x003C /* 970FX any revision*/
+#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */
+#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */
+#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */
+#define PVR_RESERVED 0x000000F0 /* reserved nibble */
+
+#define SPR_SRR0 0x01a
+#define SPR_SRR1 0x01b
+#define SPR_SPRG0 0x110
+#define SPR_SPRG1 0x111
+#define SPR_SPRG2 0x112
+#define SPR_SPRG3 0x113
+#define SPR_PVR 0x11f
+#define SPR_TBLR 0x10c
+#define SPR_TBUR 0x10d
+
+#ifdef __PPC64__
+#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \
+ ori ra,ra,value@higher; \
+ sldi ra,ra,32; \
+ oris ra,ra,value@h; \
+ ori ra,ra,value@l
+#define TLBIEL(rb) .long 0x7C000000|\
+ (rb<<11)|(274<<1)
+#define HRFID() .long 0x4C000000|\
+ (274<<1)
+#endif
+
#ifndef ASM
unsigned __getmsr(void);
void __setmsr(unsigned value);
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index d99ec6a247..179b92c1a2 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -22,6 +22,8 @@
*
*/
+#include <ppc74xx.h>
+
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index c82ab2f370..b23210c260 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -22,6 +22,8 @@
*
*/
+#include <ppc750.h>
+
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
diff --git a/src/cpu/ppc/ppc970/ppc970.inc b/src/cpu/ppc/ppc970/ppc970.inc
index 3d0f8cc3d4..b9a4013aad 100644
--- a/src/cpu/ppc/ppc970/ppc970.inc
+++ b/src/cpu/ppc/ppc970/ppc970.inc
@@ -94,16 +94,16 @@
LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL)
LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL)
addis r8,r0,0x1000
-..slbl: slbmte r6,r7
+0: slbmte r6,r7
addi r6,r6,0x1000
add r7,r7,r8
addi r7,r7,0x0001
- bdnz ..slbl
+ bdnz 0b
mtctr r5
LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL)
-..slbi: slbie r6
+1: slbie r6
add r6,r6,r8
- bdnz ..slbi
+ bdnz 1b
/*--------------------------------------------------------------------+
| Load SLB. Following is the initial memory map.
| Entry(6) ESID(36) VSID
@@ -126,11 +126,11 @@
| Invalidate all 1024 instruction and data TLBs (4 way)
+--------------------------------------------------------------------*/
addi r8,r0,0x0100
- mtspr ctr,r8
+ mtspr CTR,r8
addi r8,r0,0x0000
-..ivt: TLBIEL(r8)
+2: TLBIEL(r8)
addi r8,r8,0x1000
- bdnz ..ivt
+ bdnz 2b
ptesync
/*--------------------------------------------------------------------+
| Dcbz the page table space. Calculate SDR1 address. Store SDR1
@@ -138,13 +138,13 @@
+--------------------------------------------------------------------*/
mfspr r3,SPR_PIR
cmpi cr0,1,r3,0x0000
- bne ..cpu1
+ bne 3f
addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h
ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l
- b ..skcpu
-..cpu1: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h
+ b 4f
+3: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h
ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l
-..skcpu:addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h
+4: addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h
ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l
rlwinm r5,r4,14,14,31
cntlzw r5,r5
@@ -203,26 +203,26 @@
mtctr r3
addis r31,r0,0xF400
and r31,r31,r29
-..aF4: addi r3,r0,0x0000
+5: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
-..aF4a: lwz r4,0x0004(r3)
+6: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
- beq ..aF4s
+ beq 8f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
- blt ..aF4a
-..aF4h: b ..aF4h
-..aF4s: rlwinm r4,r31,16,4,24
+ blt 6b
+7: b 7b
+8: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01AC
stw r4,0x000C(r3)
addi r31,r31,0x1000
- bdnz ..aF4
+ bdnz 5b
/*--------------------------------------------------------------------+
| Setup 16MB of addresses in NB register space (0xF8000000).
+--------------------------------------------------------------------*/
@@ -230,61 +230,61 @@
mtctr r3
addis r31,r0,0xF800
and r31,r31,r29
-..aF8: addi r3,r0,0x0000
+9: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
-..aF8a: lwz r4,0x0004(r3)
+10: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
- beq ..aF8s
+ beq 12f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
- blt ..aF8a
-..aF8h: b ..aF8h
-..aF8s: rlwinm r4,r31,16,4,24
+ blt 10b
+11: b 11b
+12: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01AC
stw r4,0x000C(r3)
addi r31,r31,0x1000
- bdnz ..aF8
+ bdnz 9b
/*--------------------------------------------------------------------+
| Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000).
+--------------------------------------------------------------------*/
mfspr r3,SPR_HIOR
LOAD_64BIT_VAL(r4,BOOT_BASE_AS)
cmpd cr0,r3,r4
- beq ..big
+ beq 13f
addi r3,r0,0x0100
mtctr r3
addis r31,r0,0xFFF0
- b ..done
-..big: addi r3,r0,0x1000
+ b 14f
+13: addi r3,r0,0x1000
mtctr r3
addis r31,r0,0xFF00
-..done: and r31,r31,r29
-..aFF: addi r3,r0,0x0000
+14: and r31,r31,r29
+15: addi r3,r0,0x0000
ori r4,r31,0x0000
ori r5,r30,0x0000
addi r6,r0,0x000F
bl .p_ptegg
addi r6,r3,0x0080
-..aFFa: lwz r4,0x0004(r3)
+16: lwz r4,0x0004(r3)
cmpli cr0,1,r4,0x0000
- beq ..aFFs
+ beq 18f
addi r3,r3,0x0010
cmp cr0,1,r3,r6
- blt ..aFFa
-..aFFh: b ..aFFh
-..aFFs: rlwinm r4,r31,16,4,24
+ blt 16b
+17: b 17b
+18: rlwinm r4,r31,16,4,24
ori r4,r4,0x0001
stw r4,0x0004(r3)
ori r4,r31,0x01A3
stw r4,0x000C(r3)
addi r31,r31,0x1000
- bdnz ..aFF
+ bdnz 15b
/*--------------------------------------------------------------------+
| Synchronize after setting up page table.
+--------------------------------------------------------------------*/
@@ -321,16 +321,16 @@
LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS)
mfspr r5,SPR_HIOR
cmpdi cr0,r5,0x0000
- beq ..hior0
+ beq 19f
cmpd cr0,r5,r7
- beq ..hiorl
+ beq 20f
addi r8,r0,0x0000
- b ..hiors
-..hiorl:ori r8,r6,0x0000
- b ..hiors
-..hior0:mfspr r5,SPR_HID0
+ b 21f
+20: ori r8,r6,0x0000
+ b 21f
+19: mfspr r5,SPR_HID0
and r8,r5,r6
-..hiors:LOAD_64BIT_VAL(r4,HID0_PREFEAR)
+21: LOAD_64BIT_VAL(r4,HID0_PREFEAR)
andc r4,r4,r6
or r4,r4,r8
sync
diff --git a/src/mainboard/momentum/apache/Options.lb b/src/mainboard/momentum/apache/Options.lb
index 697e8133ad..548c72bcb6 100644
--- a/src/mainboard/momentum/apache/Options.lb
+++ b/src/mainboard/momentum/apache/Options.lb
@@ -138,5 +138,6 @@ default _ROMSTART=0xfff03000
## linuxBIOS C code runs at this location in RAM
default _RAMBASE=0x00100000
+default CROSS_COMPILE="powerpc64-unknown-linux-gnu-"
### End Options.lb
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 20:20:49 +0000