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-rw-r--r--src/southbridge/amd/agesa/hudson/Kconfig9
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c8
2 files changed, 13 insertions, 4 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 5cb17223f7..7e7399c090 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -247,4 +247,13 @@ if SOUTHBRIDGE_AMD_AGESA_YANGTZE
config AMD_SB_SPI_TX_LEN
int
default 64
+
+ config AZ_PIN
+ hex
+ default 0xaa
+ help
+ bit 1,0 - pin 0
+ bit 3,2 - pin 1
+ bit 5,4 - pin 2
+ bit 7,6 - pin 3
endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
index 888b83c186..f638e715dd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
@@ -266,10 +266,10 @@ FCH_DATA_BLOCK InitEnvCfgDefault = {
0, // AzaliaSnoop
0, // AzaliaDummy
{ // AZALIA_PIN
- 2, // AzaliaSdin0
- 2, // AzaliaSdin1
- 2, // AzaliaSdin2
- 2, // AzaliaSdin3
+ CONFIG_AZ_PIN & 0x3, // AzaliaSdin0
+ (CONFIG_AZ_PIN & 0xc) >> 2, // AzaliaSdin1
+ (CONFIG_AZ_PIN & 0x30) >> 4, // AzaliaSdin2
+ (CONFIG_AZ_PIN & 0xc0) >> 6, // AzaliaSdin3
},
NULL, // *AzaliaOemCodecTablePtr
NULL, // *AzaliaOemFpCodecTablePtr