diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 20 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 6 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 15 |
5 files changed, 22 insertions, 27 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 0abda49f90..f9a2b3637a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -237,14 +237,14 @@ sipi_complete: movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + post_code(0x2b) + /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2b) - /* Enable L2 cache Write-Back (WBINVD and FLUSH#). * * MSR is set when DisplayFamily_DisplayModel is one of: @@ -295,13 +295,12 @@ no_msr_11e: movl $(CACHE_AS_RAM_SIZE >> 2), %ecx rep stosl + post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x2d) - /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -319,13 +318,12 @@ no_msr_11e: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + post_code(0x2e) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - post_code(0x2e) - /* Set up the stack pointer. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp @@ -334,8 +332,8 @@ no_msr_11e: movl %esp, %ebp pushl %eax +before_romstage: post_code(0x2f) - /* Call romstage.c main function. */ call romstage_main @@ -351,7 +349,7 @@ no_msr_11e: orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x34) + post_code(0x31) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -359,18 +357,18 @@ no_msr_11e: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x35) + post_code(0x32) invd - post_code(0x36) + post_code(0x33) /* Enable cache. */ movl %cr0, %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 - post_code(0x37) + post_code(0x36) /* Disable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 3349883c53..fe595fbd22 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -179,8 +179,6 @@ before_romstage: * for setting up MTRRs. */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -196,7 +194,7 @@ before_romstage: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) /* Disable the no eviction run state */ movl $NoEvictMod_MSR, %ecx diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 093c78457d..29ff01a26a 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -150,8 +150,6 @@ clear_var_mtrrs: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr - post_code(0x27) - post_code(0x28) /* Enable cache. */ movl %cr0, %eax @@ -177,8 +175,6 @@ before_romstage: */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -194,7 +190,7 @@ before_romstage: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) /* Disable the no eviction run state */ movl $NoEvictMod_MSR, %ecx diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2757c552cb..1a1167c057 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -179,8 +179,6 @@ before_romstage: */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -196,7 +194,7 @@ before_romstage: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) /* Disable the no eviction run state */ movl $NoEvictMod_MSR, %ecx diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 9ae217c9e9..1f2445a2ab 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -47,24 +47,29 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x22) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr + post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr + post_code(0x25) + /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -91,6 +96,7 @@ clear_mtrrs: xorl %eax, %eax rep stosl + post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -113,6 +119,7 @@ clear_mtrrs: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + post_code(0x28) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -127,8 +134,8 @@ clear_mtrrs: movl %esp, %ebp pushl %eax - post_code(0x23) - +before_romstage: + post_code(0x29) /* Call romstage.c main function. */ call romstage_main @@ -137,8 +144,6 @@ clear_mtrrs: */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -154,7 +159,7 @@ clear_mtrrs: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) invd |