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-rw-r--r--src/northbridge/intel/haswell/finalize.c25
-rw-r--r--src/northbridge/intel/haswell/pcie_config.c89
-rw-r--r--src/southbridge/intel/lynxpoint/finalize.c9
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c9
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c15
-rw-r--r--src/southbridge/intel/lynxpoint/spi.c13
6 files changed, 33 insertions, 127 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 01843c9fee..58052f9952 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -21,24 +21,23 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <stdlib.h>
-#include "pcie_config.c"
#include "haswell.h"
-#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
+#define PCI_DEV_HSW PCI_DEV(0, 0, 0)
void intel_northbridge_haswell_finalize_smm(void)
{
- pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
- pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
- pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
- pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
- pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
- pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
- pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
- pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
- pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
- pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
- pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
+ pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */
+ pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */
+ pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */
+ pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */
+ pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */
+ pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */
+ pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */
+ pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */
+ pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */
+ pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */
+ pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
diff --git a/src/northbridge/intel/haswell/pcie_config.c b/src/northbridge/intel/haswell/pcie_config.c
deleted file mode 100644
index d96854e739..0000000000
--- a/src/northbridge/intel/haswell/pcie_config.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "haswell.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write32(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
-{
- u8 value = pcie_read_config8(dev, where);
- pcie_write_config8(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
-{
- u16 value = pcie_read_config16(dev, where);
- pcie_write_config16(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
-{
- u32 value = pcie_read_config32(dev, where);
- pcie_write_config32(dev, where, value | ormask);
-}
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index 796633d024..2cece13e17 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -21,7 +21,6 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/post_codes.h>
-#include <northbridge/intel/haswell/pcie_config.c>
#include <spi-generic.h>
#include "pch.h"
@@ -51,15 +50,15 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
- pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+ pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
- pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index facfc37645..12f7ab7ed2 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -39,7 +39,6 @@
#ifdef __SMM__
# include <arch/romcc_io.h>
-# include <northbridge/intel/haswell/pcie_config.c>
#else
# include <device/device.h>
# include <device/pci.h>
@@ -496,14 +495,14 @@ void intel_me_finalize_smm(void)
u32 reg32;
mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == 0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, &reg32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -516,10 +515,10 @@ void intel_me_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index c5c2c3ec15..d31e350b76 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -38,7 +38,6 @@
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/pcie_config.c>
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@@ -65,7 +64,7 @@ static u32 tseg_base = 0;
u32 smi_get_tseg_base(void)
{
if (!tseg_base)
- tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
+ tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
return tseg_base;
}
void tseg_relocate(void **ptr)
@@ -302,7 +301,7 @@ static void southbridge_gate_memory_reset(void)
u32 reg32;
u16 gpiobase;
- gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase)
return;
@@ -388,13 +387,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
}
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -625,7 +624,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
@@ -639,7 +638,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
@@ -766,7 +765,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
u32 smi_sts;
/* Update global variable pmbase */
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c
index 8eea28c88f..ec7c862beb 100644
--- a/src/southbridge/intel/lynxpoint/spi.c
+++ b/src/southbridge/intel/lynxpoint/spi.c
@@ -35,19 +35,18 @@
#ifdef __SMM__
#include <arch/romcc_io.h>
-#include <northbridge/intel/haswell/pcie_config.c>
#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pcie_read_config8(dev, reg)
+ *(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pcie_read_config16(dev, reg)
+ *(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pcie_read_config32(dev, reg)
+ *(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
- pcie_write_config8(dev, reg, val)
+ pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
- pcie_write_config16(dev, reg, val)
+ pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
- pcie_write_config32(dev, reg, val)
+ pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>