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-rw-r--r--src/northbridge/intel/nehalem/early_init.c3
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h7
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 319d81def1..1424b911e9 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -151,7 +151,8 @@ void nehalem_early_initialization(int chipset_type)
nehalem_setup_bars();
/* Device Enable */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9 | 2);
+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,
+ DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
early_cpu_init();
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 33df32fa46..bbdd290e8a 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -69,11 +69,10 @@ typedef struct {
#define D0F0_MCHBAR_HI 0x4c
#define D0F0_GGC 0x52
#define D0F0_DEVEN 0x54
+/* Note: Intel's datasheet is broken. Assume the following values are correct */
#define DEVEN_PEG60 (1 << 13)
-#define DEVEN_IGD (1 << 4)
-#define DEVEN_PEG10 (1 << 3)
-#define DEVEN_PEG11 (1 << 2)
-#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_IGD (1 << 3)
+#define DEVEN_PEG10 (1 << 1)
#define DEVEN_HOST (1 << 0)
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64