diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/veyron/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/Makefile.inc | 10 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/bootblock.c | 8 |
4 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index bbbc617d92..0ae425e2a3 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -44,6 +44,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 +config BOOT_MEDIA_SPI_BUS + int + default 2 + config DRAM_DMA_START hex default 0x10000000 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0fadefd283..359ce2f57d 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -54,6 +54,10 @@ config BOOTBLOCK_CPU_INIT # 0xFF71_3000 CBFS mapping cache (20K) # 0xFF71_7FFF End of iRAM. +config SYS_SRAM_BASE + hex "SRAM base address" + default 0xFF700000 + config SYS_SDRAM_BASE hex "SDRAM base address" default 0x00000000 diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index e0f32242a5..7d5b3a5767 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +IDBTOOL = util/rockchip/make_idb.py + #bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += timer.c @@ -43,3 +45,11 @@ ramstage-y += clock.c ramstage-y += spi.c ramstage-y += media.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + @$(IDBTOOL) --from=$< --to=$@ --enable-align diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 04afae5529..76a91d234d 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -19,12 +19,20 @@ #include <console/console.h> #include <arch/cache.h> +#include <arch/io.h> #include <bootblock_common.h> #include "timer.h" #include "clock.h" +#include "grf.h" +#include "spi.h" static void bootblock_cpu_init(void) { + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); rk3288_init_timer(); + console_init(); rkclk_init(); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); } |