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-rw-r--r--src/soc/intel/skylake/Kconfig2
-rw-r--r--src/soc/intel/skylake/Makefile.inc5
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/romstage/car_stage_fsp20.S132
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c4
6 files changed, 9 insertions, 136 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3024196f2a..23801b0ed3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -81,6 +81,8 @@ config USE_FSP2_0_DRIVER
select PLATFORM_USES_FSP2_0
select ADD_VBT_DATA_FILE
select SOC_INTEL_COMMON_GFX_OPREGION
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
config USE_FSP1_1_DRIVER
bool "Build with FSP 1.1"
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 2ef4bba143..171a9165e5 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -103,6 +103,11 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
+postcar-y += memmap.c
+postcar-y += monotonic_timer.c
+postcar-y += tsc_freq.c
+postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
+
# cpu_microcode_bins += ???
CPPFLAGS_common += -I$(src)/soc/intel/skylake
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 37e1e06fc9..6bdc3b5858 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -20,7 +20,6 @@
#include <arch/cpu.h>
#include <fsp/api.h>
-asmlinkage void *car_stage_c_entry(void);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 47c8c7e39c..7dfbd35610 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,7 +1,6 @@
verstage-y += power_state.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
-romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S
romstage-y += pmc.c
romstage-y += power_state.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S
deleted file mode 100644
index 5ef8bd61bf..0000000000
--- a/src/soc/intel/skylake/romstage/car_stage_fsp20.S
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <rules.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-
-.section ".text"
-.global car_stage_entry
-
-car_stage_entry:
-
- /* Enter the C code */
- call car_stage_c_entry
-
-/*
- * Car teardown
- */
- /*
- * eax: New stack address
- */
-
- /* Switch to the stack in RAM */
- movl %eax, %esp
-
- /* chipset_teardown_car() is expected to disable cache-as-ram. */
- call chipset_teardown_car
-
- /* Display the MTRRs */
- call soc_display_mtrrs
-
- /*
- * The stack contents are initialized in src/soc/intel/common/stack.c
- * to be the following:
- *
- * *
- * *
- * *
- * +36: MTRR mask 1 63:32
- * +32: MTRR mask 1 31:0
- * +28: MTRR base 1 63:32
- * +24: MTRR base 1 31:0
- * +20: MTRR mask 0 63:32
- * +16: MTRR mask 0 31:0
- * +12: MTRR base 0 63:32
- * +8: MTRR base 0 31:0
- * +4: Number of MTRRs to setup (described above)
- * +0: Number of variable MTRRs to clear
- */
-
- /* Clear all of the variable MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
- clr %eax
- clr %edx
-
-1:
- testl %ebx, %ebx
- jz 1f
- wrmsr /* Write MTRR base. */
- inc %ecx
- wrmsr /* Write MTRR mask. */
- inc %ecx
- dec %ebx
- jmp 1b
-
-1:
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
-2:
- testl %ebx, %ebx
- jz 2f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 2b
-2:
-
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
-
- call copy_and_run
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index fbc5fe1c53..4530190b07 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -115,7 +115,7 @@ static void save_dimm_info(void)
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-asmlinkage void *car_stage_c_entry(void)
+asmlinkage void car_stage_entry(void)
{
bool s3wake;
struct postcar_frame pcf;
@@ -170,7 +170,7 @@ asmlinkage void *car_stage_c_entry(void)
postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
}
static void cpu_flex_override(FSP_M_CONFIG *m_cfg)