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-rw-r--r--src/include/device/smbus_host.h2
-rw-r--r--src/soc/intel/broadwell/include/soc/smbus.h1
-rw-r--r--src/soc/intel/broadwell/smbus.c3
-rw-r--r--src/soc/intel/cannonlake/include/soc/smbus.h4
-rw-r--r--src/soc/intel/common/block/smbus/smbus.c4
-rw-r--r--src/soc/intel/denverton_ns/include/soc/smbus.h2
-rw-r--r--src/soc/intel/icelake/include/soc/smbus.h4
-rw-r--r--src/soc/intel/skylake/include/soc/smbus.h3
-rw-r--r--src/soc/intel/tigerlake/include/soc/smbus.h2
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
-rw-r--r--src/southbridge/intel/bd82x6x/smbus.c4
-rw-r--r--src/southbridge/intel/common/smbus.c5
-rw-r--r--src/southbridge/intel/common/smbus.h2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h1
-rw-r--r--src/southbridge/intel/ibexpeak/smbus.c4
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h1
-rw-r--r--src/southbridge/intel/lynxpoint/smbus.c4
17 files changed, 14 insertions, 33 deletions
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h
index 071eef0ff2..cb31d02d33 100644
--- a/src/include/device/smbus_host.h
+++ b/src/include/device/smbus_host.h
@@ -35,6 +35,6 @@ int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf);
/* Upstream API */
void smbus_host_reset(uintptr_t base);
-
+void smbus_set_slave_addr(uintptr_t base, u8 slave_address);
#endif
diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h
index 40aaf438a8..ed37373360 100644
--- a/src/soc/intel/broadwell/include/soc/smbus.h
+++ b/src/soc/intel/broadwell/include/soc/smbus.h
@@ -22,7 +22,6 @@
#define SMB_BASE 0x20
#define HOSTC 0x40
#define HST_EN (1 << 0)
-#define SMB_RCV_SLVA 0x09
/* SMBus I/O bits. */
#define SMBHSTSTAT 0x0
diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c
index c32e31d6a9..0ac2ffc388 100644
--- a/src/soc/intel/broadwell/smbus.c
+++ b/src/soc/intel/broadwell/smbus.c
@@ -24,7 +24,6 @@
#include <soc/iomap.h>
#include <soc/ramstage.h>
#include <soc/smbus.h>
-#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h>
static void pch_smbus_init(struct device *dev)
@@ -40,7 +39,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
- outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index e3d93a2a54..54d0d6cfbf 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -19,10 +19,6 @@
#ifndef _SOC_CANNONLAKE_SMBUS_H_
#define _SOC_CANNONLAKE_SMBUS_H_
-/* IO and MMIO registers under primary BAR */
-/* Set address for PCH as SMBus slave role */
-#define SMB_RCV_SLVA 0x09
-
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index ce75f3a891..a99efafe85 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -13,14 +13,12 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <device/device.h>
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/smbus.h>
-#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h>
#include "smbuslib.h"
@@ -63,7 +61,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
- outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static void smbus_read_resources(struct device *dev)
diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h
index 5dbeecc0cf..5668440af3 100644
--- a/src/soc/intel/denverton_ns/include/soc/smbus.h
+++ b/src/soc/intel/denverton_ns/include/soc/smbus.h
@@ -25,7 +25,7 @@
#define HST_EN (1 << 0)
#define HOSTC_SMI_EN (1 << 1)
#define HOSTC_I2C_EN (1 << 2)
-#define SMB_RCV_SLVA 0x09
+
/* SMBUS TCO base address. */
#define TCOBASE 0x50
#define MASK_TCOBASE 0xffe0
diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h
index f4f5b11288..9d8fe46b64 100644
--- a/src/soc/intel/icelake/include/soc/smbus.h
+++ b/src/soc/intel/icelake/include/soc/smbus.h
@@ -16,10 +16,6 @@
#ifndef _SOC_ICELAKE_SMBUS_H_
#define _SOC_ICELAKE_SMBUS_H_
-/* IO and MMIO registers under primary BAR */
-/* Set address for PCH as SMBus slave role */
-#define SMB_RCV_SLVA 0x09
-
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index aad57aabb6..ee257ea613 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -19,9 +19,6 @@
#ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_
-/* PCI Configuration Space (D31:F3): SMBus */
-#define SMB_RCV_SLVA 0x09
-
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h
index 9226fba4e1..50ea044e53 100644
--- a/src/soc/intel/tigerlake/include/soc/smbus.h
+++ b/src/soc/intel/tigerlake/include/soc/smbus.h
@@ -23,8 +23,6 @@
#define _SOC_TIGERLAKE_SMBUS_H_
/* IO and MMIO registers under primary BAR */
-/* Set address for PCH as SMBus slave role */
-#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 089d4586bf..5f353af1ee 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -238,7 +238,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
#define HOSTC 0x40
-#define SMB_RCV_SLVA 0x09
/* HOSTC bits */
#define I2C_EN (1 << 2)
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 0a9c17598e..b011c493a7 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -20,8 +20,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h>
#include "pch.h"
@@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
- outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index f6805ad50f..d253ae7e04 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -101,6 +101,11 @@ void smbus_host_reset(uintptr_t base)
host_and_or(base, SMBHSTSTAT, 0xff, 0);
}
+void smbus_set_slave_addr(uintptr_t base, u8 slave_address)
+{
+ host_outb(base, SMB_RCV_SLVA, slave_address);
+}
+
static int host_completed(u8 status)
{
if (status & SMBHSTSTS_HOST_BUSY)
diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h
index 20443e1060..e72203e46e 100644
--- a/src/southbridge/intel/common/smbus.h
+++ b/src/southbridge/intel/common/smbus.h
@@ -32,4 +32,6 @@
#define SMBUS_PIN_CTL 0xf
#define SMBSLVCMD 0x11
+#define SMB_RCV_SLVA SMBTRNSADD
+
#endif
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 5785ef1a67..529b7a2e83 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -232,7 +232,6 @@ void pch_enable(struct device *dev);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
#define HOSTC 0x40
-#define SMB_RCV_SLVA 0x09
/* HOSTC bits */
#define I2C_EN (1 << 2)
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 9168cffb24..accbe68bd0 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -20,8 +20,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h>
#include "pch.h"
@@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
- outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d83dd17275..71f42ea723 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -440,7 +440,6 @@ void mainboard_config_superio(void);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
#define HOSTC 0x40
-#define SMB_RCV_SLVA 0x09
/* HOSTC bits */
#define I2C_EN (1 << 2)
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index 24beaf2fde..ff659b837a 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -20,8 +20,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h>
#include "pch.h"
@@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
- outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 15:48:54 +0000