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-rw-r--r--src/cpu/amd/car/cache_as_ram.inc19
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc13
-rw-r--r--src/cpu/via/car/cache_as_ram.inc41
-rw-r--r--src/include/cpu/x86/mtrr.h3
4 files changed, 35 insertions, 41 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 488aed32d1..f43febe0d4 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -90,7 +90,7 @@ cache_as_ram_setup:
*/
movl $0x1b, %ecx
rdmsr
- bt $8, %eax /* BSC */
+ bt $8, %eax /* BSP */
jnc CAR_FAM10_out
/* Enable RT tables on BSP. */
@@ -135,15 +135,14 @@ CAR_FAM10_out:
wrmsr
#if CONFIG_MMCONF_SUPPORT
- /* Set MMIO Config space BAR. */
+ /* Set MMIO config space BAR. */
movl $MSR_MCFG_BASE, %ecx
rdmsr
-
andl $(~(0xfff00000 | (0xf << 2))), %eax
- orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax
+ orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax
+ orl $((8 << 2) | (1 << 0)), %eax
andl $(~(0x0000ffff)), %edx
orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
-
wrmsr
#endif
@@ -216,7 +215,7 @@ clear_fixed_var_mtrr_out:
.endm
/*
- * size is the cache size in bytes we want to use for CAR.
+ * carsize is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
@@ -289,7 +288,7 @@ wbcache_post_fam10_setup:
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
+ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr
/* Enable the MTRRs and IORRs in SYSCFG. */
@@ -302,7 +301,7 @@ wbcache_post_fam10_setup:
/* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
jmp_if_k8(fam10_end_part1)
@@ -310,7 +309,7 @@ wbcache_post_fam10_setup:
/* So we need to check if it is BSP. */
movl $0x1b, %ecx
rdmsr
- bt $8, %eax /* BSC */
+ bt $8, %eax /* BSP */
jnc CAR_FAM10_ap
fam10_end_part1:
@@ -365,7 +364,7 @@ CAR_FAM10_ap:
movl $0xc001001f, %ecx /* NB_CFG_MSR */
rdmsr
movl %edi, %ecx /* CoreID bits */
- bt $(54-32), %edx
+ bt $(54 - 32), %edx
jc roll_cfg
rolb %cl, %bl
roll_cfg:
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index ea455bfce3..98d227db2f 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -110,7 +110,7 @@ NotHtProcessor:
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
+ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr
/* Clear all MTRRs. */
@@ -169,7 +169,7 @@ clear_fixed_var_mtrr_out:
.endm
/*
- * size is the cache size in bytes we want to use for CAR.
+ * carsize is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
@@ -221,8 +221,7 @@ clear_fixed_var_mtrr_out:
*/
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
@@ -233,7 +232,7 @@ clear_fixed_var_mtrr_out:
/* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
/* Read the range with lodsl. */
@@ -303,7 +302,7 @@ lout:
pushl %eax /* BIST */
call main
- /* We don't need CAR for now on. */
+ /* We don't need CAR from now on. */
/* Disable cache. */
movl %cr0, %eax
@@ -332,7 +331,7 @@ lout:
/* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
/* Clear boot_complete flag. */
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 2ae1f52a22..6389a3833f 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -45,7 +45,7 @@ CacheAsRam:
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
+ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr
/* Clear all MTRRs. */
@@ -100,8 +100,7 @@ clear_fixed_var_mtrr_out:
*/
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
@@ -109,13 +108,16 @@ clear_fixed_var_mtrr_out:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
+ /* Set the default memory type and enable fixed and variable MTRRs. */
+ /* TODO: Or also enable fixed MTRRs? Bug in the code? */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */
+ movl $(MTRRdefTypeEn), %eax
wrmsr
+ /* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
/* Read the range with lodsl. */
@@ -186,27 +188,24 @@ testok:
* want to go back.
*/
- /* We don't need CAR for now on. */
+ /* We don't need CAR from now on. */
/* Disable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
- /*
- * Set the default memory type and disable fixed and enable
- * variable MTRRs.
- */
+ /* Set the default memory type and enable variable MTRRs. */
+ /* TODO: Or also enable fixed MTRRs? Bug in the code? */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */
+ movl $(MTRRdefTypeEn), %eax
wrmsr
/* Enable caching for first 1M using variable MTRR. */
movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx
- movl $(0 | 6), %eax
- // movl $(0 | MTRR_TYPE_WRBACK), %eax
+ movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr
/*
@@ -223,8 +222,7 @@ testok:
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(0x80000 | 6), %eax
- orl $(0 | 6), %eax
+ movl $(0x80000 | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
@@ -234,8 +232,7 @@ testok:
movl $MTRRphysBase_MSR(2), %ecx
xorl %edx, %edx
- movl $(0xc0000 | 6), %eax
- orl $(0 | 6), %eax
+ movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
@@ -246,21 +243,17 @@ testok:
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(3), %ecx
xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE,%eax
- orl $(0 | 6), %eax
+ movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(3), %ecx
xorl %edx, %edx
- movl $CONFIG_XIP_ROM_SIZE, %eax
- decl %eax
- notl %eax
- orl $(0 | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
/* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
invd
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 667c7ad916..e79c90ea85 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -15,6 +15,9 @@
#define MTRRcap_MSR 0x0fe
#define MTRRdefType_MSR 0x2ff
+#define MTRRdefTypeEn (1 << 11)
+#define MTRRdefTypeFixEn (1 << 10)
+
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 19:33:54 +0000