4 files changed, 5 insertions, 18 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 096f8722df..0693d4d564 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -26,7 +26,6 @@
 void i82371eb_enable(device_t dev);
 #endif
 
-#define PCICMD		0x04	/* PCI Command Register */
 #define XBCS		0x4e	/* X-Bus Chip Select register */
 
 /* SMBus */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index ab0b51e52e..7ef268d654 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -49,9 +49,9 @@ static void enable_smbus(void)
 	pci_write_config8(dev, SMBHSTCFG, reg8);
 
 	/* Enable access to the SMBus I/O space. */
-	reg16 = pci_read_config16(dev, PCICMD);
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
 	reg16 |= IOSE;
-	pci_write_config16(dev, PCICMD, reg16);
+	pci_write_config16(dev, PCI_COMMAND, reg16);
 
 	/* Clear any lingering errors, so the transaction will run. */
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c
index 2c5b0c68d2..516edd66fc 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_ide.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_ide.c
@@ -35,9 +35,7 @@
 static void ide_init(struct device *dev)
 {
 	uint16_t reg;
-	struct southbridge_intel_i82371eb_config *conf;
-
-	conf = dev->chip_info;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
 
 	/* Enable/disable the primary IDE interface. */
 	reg = pci_read_config16(dev, IDETIM_PRI);
@@ -62,18 +60,13 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, IDETIM_SEC, reg);
 }
 
-/* There are no subsystem IDs on the Intel 82371EB. */
-static struct pci_operations lops_pci = {
-	// .set_subsystem = 0,
-};
-
 static struct device_operations ide_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= ide_init,
 	.scan_bus		= 0,
-	.ops_pci		= &lops_pci,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
 };
 
 static struct pci_driver ide_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index cc47f78649..e8df072045 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -27,11 +27,6 @@
 static struct smbus_bus_operations lops_smbus_bus = {
 };
 
-/* There are no subsystem IDs on the Intel 82371EB. */
-static struct pci_operations lops_pci = {
-	// .set_subsystem = 0,
-};
-
 static struct device_operations smbus_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
@@ -39,7 +34,7 @@ static struct device_operations smbus_ops = {
 	.init			= 0,
 	.scan_bus		= scan_static_bus,
 	// .enable		= i82371eb_enable,	// TODO: Needed?
-	.ops_pci		= &lops_pci,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
 	.ops_smbus_bus		= &lops_smbus_bus,
 };