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-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c3c6c07ebf..75387624cb 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -30,12 +30,13 @@ SECTIONS
SRAM_START(0x9a000000)
BOOTBLOCK(0x9a000000, 16K)
ROMSTAGE(0x9a004000, 36K)
- STACK(0x9a01c000, 8K)
- PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
+ CBFS_CACHE(0x9a00d000, 76K)
SRAM_END(0x9a020000)
- /* Let's use SRAM for CBFS cache. */
- CBFS_CACHE(0x9b000000, 64K)
+ /* Let's use SRAM for stack and CBMEM console. */
+ STACK(0x9b000000, 8K)
+ PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
+
/* DMA coherent area: end of available DRAM, uncached */
DMA_COHERENT(0xAFF00000, 1M)
}