diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 11 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 8 |
2 files changed, 7 insertions, 12 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 06079dd98b..da93175b21 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1975,10 +1975,6 @@ static void root_complex_enable_dev(struct device *dev) /* Do not delay UMA setup, as a device on the PCI bus may evaluate the global uma_memory variables already in its enable function. */ if (!done) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3) - save_mct_information_to_nvram(); -#endif - setup_bsp_ramtop(); setup_uma_memory(); done = 1; @@ -1992,7 +1988,14 @@ static void root_complex_enable_dev(struct device *dev) } } +static void root_complex_finalize(void *chip_info) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3) + save_mct_information_to_nvram(); +#endif +} + struct chip_operations northbridge_amd_amdfam10_root_complex_ops = { CHIP_NAME("AMD Family 10h/15h Root Complex") .enable_dev = root_complex_enable_dev, + .final = root_complex_finalize, }; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index fe7707591e..6589a39943 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -1132,11 +1132,6 @@ int8_t save_mct_information_to_nvram(void) s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); s3nv_offset += CONFIG_S3_DATA_SIZE; - /* Set temporary SPI MMIO address */ - device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - uint32_t spi_mmio_prev = pci_read_config32(lpc_dev, 0xa0); - pci_write_config32(lpc_dev, 0xa0, (spi_mmio_prev & 0x1f) | 0xf0000000); - /* Initialize SPI and detect devices */ spi_init(); flash = spi_flash_probe(0, 0); @@ -1160,9 +1155,6 @@ int8_t save_mct_information_to_nvram(void) flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); - /* Restore SPI MMIO address */ - pci_write_config32(lpc_dev, 0xa0, spi_mmio_prev); - /* Allow training bypass if DIMM configuration is unchanged on next boot */ nvram = 1; set_option("allow_spd_nvram_cache_restore", &nvram); |