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-rw-r--r--src/northbridge/intel/ironlake/ironlake.h2
-rw-r--r--src/northbridge/intel/ironlake/registers/host_bridge.h (renamed from src/northbridge/intel/ironlake/hostbridge_regs.h)6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 73f430ff48..93653c9658 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -43,7 +43,7 @@
/* Device 0:0.0 PCI configuration space (Host Bridge) */
-#include "hostbridge_regs.h"
+#include "registers/host_bridge.h"
/*
* Generic Non-Core Registers
diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/registers/host_bridge.h
index a681734c13..0322a515cc 100644
--- a/src/northbridge/intel/ironlake/hostbridge_regs.h
+++ b/src/northbridge/intel/ironlake/registers/host_bridge.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__
-#define __IRONLAKE_HOSTBRIDGE_REGS_H__
+#ifndef __IRONLAKE_REGISTERS_HOST_BRIDGE_H__
+#define __IRONLAKE_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40
#define MCHBAR 0x48
@@ -28,4 +28,4 @@
#define CAPID0 0xe0
-#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */
+#endif /* __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ */