diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_flash.c | 66 | ||||
| -rw-r--r-- | src/soc/intel/common/spi_flash.c | 66 | ||||
| -rw-r--r-- | src/soc/intel/common/spi_flash.h | 50 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 |
9 files changed, 56 insertions, 135 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4ec1c982c5..26a8a5554c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -91,7 +91,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_GFX_OPREGION - select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b95c8430c0..beb812b080 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -69,7 +69,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART - select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8f2b60c4db..18a34b335c 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -12,10 +12,6 @@ config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n -config SOC_INTEL_COMMON_SPI_FLASH_PROTECT - bool - default n - if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 450473006f..50f7e9e555 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -21,7 +21,6 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_FLASH_PROTECT) += spi_flash.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 1d3a3c8b51..288e0c4389 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -22,7 +22,6 @@ #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> #include <lib.h> -#include <soc/intel/common/spi_flash.h> #include <soc/pci_devs.h> #include <spi_flash.h> #include <spi-generic.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 6dac24e4e6..4579b19151 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> -#include <soc/intel/common/spi_flash.h> #include <soc/pci_devs.h> #include <spi_flash.h> #include <string.h> @@ -318,15 +317,6 @@ static int fast_spi_flash_probe(const struct spi_slave *dev, return 0; } -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - BOILERPLATE_CREATE_CTX(ctx); - - info->base = ctx->mmio_base + SPIBAR_FPR_BASE; - info->max = SPIBAR_FPR_MAX; - return 0; -} - /* * Minimal set of commands to read WPSR from FAST_SPI. * Returns 0 on success, < 0 on failure. @@ -362,8 +352,64 @@ static int fast_spi_flash_ctrlr_setup(const struct spi_slave *dev) return 0; } +#define SPI_FPR_SHIFT 12 +#define SPI_FPR_MASK 0x7fff +#define SPI_FPR_BASE_SHIFT 0 +#define SPI_FPR_LIMIT_SHIFT 16 +#define SPI_FPR_RPE (1 << 15) /* Read Protect */ +#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR(base, limit) \ + (((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\ + ((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT)) + +/* + * Protect range of SPI flash defined by [start, start+size-1] using Flash + * Protected Range (FPR) register if available. + */ +static int fast_spi_flash_protect(const struct spi_flash *flash, + const struct region *region) +{ + u32 start = region_offset(region); + u32 end = start + region_sz(region) - 1; + u32 reg; + int fpr; + uintptr_t fpr_base; + BOILERPLATE_CREATE_CTX(ctx); + + fpr_base = ctx->mmio_base + SPIBAR_FPR_BASE; + + /* Find first empty FPR */ + for (fpr = 0; fpr < SPIBAR_FPR_MAX; fpr++) { + reg = read32((void *)fpr_base); + if (reg == 0) + break; + fpr_base += sizeof(uint32_t); + } + + if (fpr >= SPIBAR_FPR_MAX) { + printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); + return -1; + } + + /* Set protected range base and limit */ + reg = SPI_FPR(start, end) | SPI_FPR_WPE; + + /* Set the FPR register and verify it is protected */ + write32((void *)fpr_base, reg); + reg = read32((void *)fpr_base); + if (!(reg & SPI_FPR_WPE)) { + printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); + return -1; + } + + printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", + __func__, fpr, start, end); + return 0; +} + const struct spi_ctrlr fast_spi_flash_ctrlr = { .setup = fast_spi_flash_ctrlr_setup, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, .flash_probe = fast_spi_flash_probe, + .flash_protect = fast_spi_flash_protect, }; diff --git a/src/soc/intel/common/spi_flash.c b/src/soc/intel/common/spi_flash.c deleted file mode 100644 index c7717c9fe9..0000000000 --- a/src/soc/intel/common/spi_flash.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include "spi_flash.h" - -/* - * Protect range of SPI flash defined by [start, start+size-1] using Flash - * Protected Range (FPR) register if available. - */ -int spi_flash_protect(u32 start, u32 size) -{ - struct fpr_info fpr_info; - u32 end = start + size - 1; - u32 reg; - int fpr; - uintptr_t fpr_base; - - if (spi_flash_get_fpr_info(&fpr_info) == -1) { - printk(BIOS_ERR, "ERROR: FPR Info not found!\n"); - return -1; - } - - fpr_base = fpr_info.base; - - /* Find first empty FPR */ - for (fpr = 0; fpr < fpr_info.max; fpr++) { - reg = read32((void *)fpr_base); - if (reg == 0) - break; - fpr_base += sizeof(uint32_t); - } - - if (fpr >= fpr_info.max) { - printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); - return -1; - } - - /* Set protected range base and limit */ - reg = SPI_FPR(start, end) | SPI_FPR_WPE; - - /* Set the FPR register and verify it is protected */ - write32((void *)fpr_base, reg); - reg = read32((void *)fpr_base); - if (!(reg & SPI_FPR_WPE)) { - printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); - return -1; - } - - printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", - __func__, fpr, start, end); - return 0; -} diff --git a/src/soc/intel/common/spi_flash.h b/src/soc/intel/common/spi_flash.h deleted file mode 100644 index d6bb079dbb..0000000000 --- a/src/soc/intel/common/spi_flash.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __INTEL_COMMON_SPI_FLASH_H__ -#define __INTEL_COMMON_SPI_FLASH_H__ - -#define SPI_FPR_SHIFT 12 -#define SPI_FPR_MASK 0x7fff -#define SPI_FPR_BASE_SHIFT 0 -#define SPI_FPR_LIMIT_SHIFT 16 -#define SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ -#define SPI_FPR(base, limit) \ - (((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\ - ((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT)) - -struct fpr_info { - /* Offset of first FPR register */ - uintptr_t base; - /* Maximum number of FPR registers */ - uint8_t max; -}; - -/* - * SoC is expected to implement this function to provide address of first FPR - * register and max count of FPR registers. - * - * On success return 0 else -1. - */ -int spi_flash_get_fpr_info(struct fpr_info *info); - -/* - * Protect range of SPI flash defined by [start, start+size-1] using Flash - * Protected Range (FPR) register if available. - */ -int spi_flash_protect(u32 start, u32 size); - -#endif /* __INTEL_COMMON_SPI_FLASH_H__ */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2dbf4a2669..20665713d9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -82,7 +82,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SMM_TSEG select SMP select SSE2 |