summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/purism/librem_whl/ramstage.c3
-rw-r--r--src/mainboard/purism/librem_whl/romstage.c9
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c
index 07ede66505..56ed1b7844 100644
--- a/src/mainboard/purism/librem_whl/ramstage.c
+++ b/src/mainboard/purism/librem_whl/ramstage.c
@@ -10,7 +10,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
size_t num_gpios;
const struct pad_config *gpio_table = variant_gpio_table(&num_gpios);
cnl_configure_pads(gpio_table, num_gpios);
-
- /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */
- params->SataSpeedLimit = 2;
}
diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c
index 9f8d600950..3a3ca6b491 100644
--- a/src/mainboard/purism/librem_whl/romstage.c
+++ b/src/mainboard/purism/librem_whl/romstage.c
@@ -48,5 +48,12 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+ FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
+ cannonlake_memcfg_init(mem_cfg, &memcfg);
+
+ /* Enable and set SATA HSIO adjustments for ports 0 and 2 */
+ mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1;
+ mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1;
+ mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2;
+ mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1;
}